TDA4VM21 datasheet(268/331 Pages) TI

268 / 331 page

6.9.5.19.1.3 High Speed DDR Mode

Table 6-83, Figure 6-94, Table 6-84, and Figure 6-95 present timing requirements and switching characteristics

for MMC0 – High Speed DDR Mode.

Table 6-83. MMC0 Timing Requirements – High Speed DDR Mode

see Figure 6-94

NO.

MIN

MAX

UNIT

HSDDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

HSDDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

2.5

HSDDR3

tsu(dV-clkV)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition

0.74

HSDDR4

th(clkV-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition

1.67

Figure 6-94. MMC0 – High Speed DDR Mode – Receive Mode

Table 6-84. MMC0 Switching Characteristics – High Speed DDR Mode

see Figure 6-95

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSDDR5

tc(clk)

Cycle time, MMC0_CLK

HSDDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSDDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSDDR8

td(clkH-cmdV)

Delay time, MMC0_CLK rising edge to MMC0_CMD transition

3.4

9.72

HSDDR9

td(clkV-dV)

Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition

2.9

6.6

Figure 6-95. MMC0 – High Speed DDR Mode – Transmit Mode

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

268

Submit Document Feedback

Product Folder Links: TDA4VM-Q1 TDA4VM

TDA4VM21 Datasheet(PDF) 268 Page - Texas Instruments

TDA4VM21 Datasheet(HTML) 268 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL