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TDA4VM21 Datasheet(PDF) 269 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 269 Page - Texas Instruments |
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269 / 331 page ![]() 6.9.5.19.1.4 HS200 Mode Table 6-85 and Figure 6-96 present switching characteristics for MMC0 – HS200 Mode. Table 6-85. MMC0 Switching Characteristics – HS200 Mode see Figure 6-96 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 200 MHz HS2005 tc(clk) Cycle time, MMC0_CLK 5 ns HS2006 tw(clkH) Pulse duration, MMC0_CLK high 2.08 ns HS2007 tw(clkL) Pulse duration, MMC0_CLK low 2.08 ns HS2008 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.12 3.16 ns HS2009 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition 1.12 3.16 ns Figure 6-96. MMC0 – HS200 Mode – Transmit Mode 6.9.5.19.2 MMC1/2 - SD/SDIO Interface MMC1 and MMC2 interfaces are compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and they support the following SD Card applications: • Default speed • High speed • UHS–I SDR12 • UHS–I SDR25 • UHS–I SDR50 • UHS–I SDR104 • UHS–I DDR50 Table 6-86 presents the required DLL software configuration settings for MMC1 timing modes. Table 6-86. MMC1/2 DLL Delay Mapping for All Timing Modes REGISTER NAME MMCSD12_SS_PHY_CTRL_4_REG MMCSD12_SS_PHY_CTRL_5_REG BIT FIELD [20] [15:12] [8] [4:0] [2:0] BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION Default Speed 4-bit PHY operating 3.3 V, 25 MHz 0x1 0x1 0x0 0x0 0x7 High Speed 4-bit PHY operating 3.3 V, 50 MHz 0x1 0x1 0x0 0x0 0x7 UHS-I SDR12 4-bit PHY operating 1.8 V, 25 MHz 0x1 0xF 0x0 0x0 0x7 UHS-I SDR25 4-bit PHY operating 1.8 V, 50 MHz 0x1 0xF 0x0 0x0 0x7 www.ti.com TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 269 Product Folder Links: TDA4VM-Q1 TDA4VM |
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