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TDA4VM21 Datasheet(PDF) 271 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 271 Page - Texas Instruments |
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271 / 331 page  6.9.5.19.2.1 Default Speed Mode Table 6-88, Figure 6-97, Table 6-89, and Figure 6-98 present timing requirements and switching characteristics for MMC1/2 – Default Speed Mode. Table 6-88. MMC1/2 Timing Requirements – Default Speed Mode see Figure 6-97 NO. MIN MAX UNIT DS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.55 ns DS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 4.65 ns DS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.55 ns DS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 4.65 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLK x M [ ]_ MC CMD x MMC DAT [ ]_ [3:0] x DS1 DS2 DS3 DS4 Figure 6-97. MMC1/2 – Default Speed – Receive Mode Table 6-89. MMC1/2 Switching Characteristics – Default Speed Mode see Figure 6-98 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 25 MHz DS5 tc(clk) Cycle time, MMC[x]_CLK 40 ns DS6 tw(clkH) Pulse duration, MMC[x]_CLK high 18.7 ns DS7 tw(clkL) Pulse duration, MMC[x]_CLK low 18.7 ns DS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition -2.93 3.63 ns DS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition -2.93 3.63 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] D 5 S D 7 S D 8 S D 9 S DS6 Figure 6-98. MMC1/2 – Default Speed – Transmit Mode www.ti.com TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 271 Product Folder Links: TDA4VM-Q1 TDA4VM |
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