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TDA4VM21 Datasheet(PDF) 277 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 277 Page - Texas Instruments |
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277 / 331 page  6.9.5.19.2.7 UHS–I SDR104 Mode Table 6-98, and Figure 6-107 present switching characteristics for MMC1/2 – UHS-I SDR104 Mode. Table 6-98. MMC1/2 Switching Characteristics – UHS-I SDR104 Mode see Figure 6-107 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 200 MHz SDR1045 tc(clk) Cycle time, MMC[x]_CLK 5 ns SDR1046 tw(clkH) Pulse duration, MMC[x]_CLK high 2.08 ns SDR1047 tw(clkL) Pulse duration, MMC[x]_CLK low 2.08 ns SDR1048 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.12 3.16 ns SDR1049 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 1.12 3.16 ns A. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR1045 SDR1047 SDR1046 SDR1048 SDR1049 SDR1048 SDR1049 Figure 6-107. MMC1/2 – UHS-I SDR104 – Transmit Mode 6.9.5.20 CPTS Table 6-99 represents CPTS timing conditions. Table 6-99. CPTS Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 10 pF Section 6.9.5.20.1, Section 6.9.5.20.2, Figure 6-108, and Figure 6-109 present timing requirements and switching characteristics of the CPTS interface. 6.9.5.20.1 CPTS Timing Requirements see Figure 6-108 NO. MIN MAX UNIT T1 tw(HWnTSPUSHH) Pulse duration, HWnTSPUSH(2) high 12P + 2(1) ns T2 tw(HWnTSPUSHL) Pulse duration, HWnTSPUSH(2) low 12P + 2(1) ns T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45 * T(3) ns T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45 * T(3) ns (1) P = functional clock period in ns. (2) In HWnTSPUSH, n = 1 to 2. (3) T = RFT_CLK period in ns. www.ti.com TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 277 Product Folder Links: TDA4VM-Q1 TDA4VM |
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