TDA4VM21 datasheet(281/331 Pages) TI

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OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_05

O 9

O20

Figure 6-110. OSPI Timing Requirements – SDR, Internal Clock and Internal Pad Loopback Clock

OSPI_DQS

OSPI_TIMING_06

O21

O 2

OSPI_D[i:0]

Figure 6-111. OSPI Timing Requirements – SDR, External Loopback Clock

6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

7.5

tw(CLKL)

Pulse duration, CLK low

-0.3+0.475*P

(2)

tw(CLKH)

Pulse duration, CLK high

-0.3+0.475*P

(2)

O10 td(CLK-CSn)

Delay time, CLK rising edge to CSn active edge

1.8V

0.475 * P +

0.975 * N * R

(2) (3) (5)

0.475 * P +

0.975 * N * R

+ 1 (3) (3) (5)

3.3V

0.475 * P +

0.975 * N * R

(2) (3) (5)

0.475 * P +

0.975 * N * R

+ 1 (2) (3) (5)

O11 td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

0.475 * P +

0.975 * N * R

- 1 (2) (4) (5)

0.475 * P +

0.975 * N * R

+ 1 (2) (4) (5)

3.3V

-1+0.475 * P

+ 0.975 * N *

R (2) (4) (5)

1+0.475 * P +

0.975 * N * R

(2) (4) (5)

O12 td(CLK-D)

Delay time, CLK active edge to D[i:0]

transition(1)

1.8V

-1.16

1.25

3.3V

-1.33

1.51

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

P = CLK cycle time = SCLK period

(3)

N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5)

R = refclk

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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TDA4VM21 Datasheet(PDF) 281 Page - Texas Instruments

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