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OSPI_CLK

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

OSPI_D[i:0]

Figure 6-112. OSPI Switching Characteristics – SDR

Section 6.9.5.21.1.2.3, Section 6.9.5.21.1.2.1, Section 6.9.5.21.1.2.2, Section 6.9.5.21.1.2.2, and Figure 6-111

presents timing requirements for OSPI DDR and SDR Mode.

6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode

Table 6-102. OSPI DLL Delay Mapping - DDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT

FIELD

DELAY VALUE

OSPI0

OSPI1

Transmit

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x40

0x41

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x3C

0x3E

Receive

1.8V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x13

0x15

3.3V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x1E

All other modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

NO. PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O15 tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK (DQS)

edge(1)

1.8V, External Board Loopback

0.52

3.3V, External Board Loopback

1.97

O16 th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK (DQS)

edge(1)

1.8V, External Board Loopback

1.24 (2)

3.3V, External Board Loopback

1.44 (2)

O17 tsu(D-DQS)

Setup time, DQS edge to D[i:0] transition(1)

1.8V, DQS

-0.46

3.3V, DQS

-0.66

O18 th(DQS-D)

Hold time, DQS edge to D[i:0] transition(1)

1.8V, DQS

3.59

3.3V, DQS

8.89

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the

SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to Section 8.3.2 for more

details.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

Figure 6-113. OSPI Timing Requirements – DDR, External Loopback Clock and DQS

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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