TDA4VM21 datasheet(283/331 Pages) TI

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6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

tw(CLKL)

Pulse duration, CLK low

0.475*P - 0.3

(2)

tw(CLKH)

Pulse duration, CLK high

0.475*P - 0.3

(2)

td(CLK-CSn)

Delay time, CSn active edge to CLK rising edge

1.8V

0.475 * P +

0.975 * N * R

(2) (3) (5)

0.475 * P +

0.975 * N * R

+ 1 (2) (3) (5)

3.3V

0.475 * P +

0.975 * N * R

(2) (3) (5)

0.475 * P +

0.975 * N * R

+ 1(2) (3) (5)

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

0.475 * P +

0.975 * N * R

- 7(2) (4) (5)

0.475 * P +

0.975 * N * R

(2) (4) (5)

3.3V, OSPI0 DDR TX;

3.3V, OSPI1 DDR TX

0.475 * P +

0.975 * N * R

- 7(2) (4) (5)

0.475 * P +

0.975 * N * R

(2) (4) (5)

td(CLK-D)

Delay time, CLK active edge to D[i:0]

transition(1)

1.8V, OSPI0 DDR TX;

1.8V, OSPI1 DDR TX

-7.71

-1.56

3.3V, OSPI0 DDR TX;

3.3V, OSPI1 DDR TX

-7.71

-1.56

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

P = CLK cycle time = SCLK period

(3)

N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5)

R = refclk

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 6-114. OSPI Switching Characteristics – DDR

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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