TDA4VM21 datasheet(286/331 Pages) TI

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6.9.5.21.2.2 OSPI Tap DDR Timing

Table 6-105, Figure 6-117, Table 6-106, and Figure 6-118 present timing requirements and switching

characteristics for OSPI0 Tap DDR Mode.

Table 6-105. OSPI Timing Requirements – Tap DDR Mode

see Figure 6-117

NO.

MODE

MIN

MAX

UNIT

O13

tsu(D-CLK)

Setup time, OSPI0/1_D[7:0] valid before

active OSPI0/1_CLK edge

No Loopback

(12.04 -

(0.975T(1)R(2)))

O14

th(CLK-D)

Hold time, OSPI0/1_D[7:0] valid after

active OSPI0/1_CLK edge

No Loopback

(1.84 +

(0.975T(1)R(2)))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = reference clock cycle time in ns

OSPI_CLK

O14

O13

OSPI_TIMING_03

OSPI_D[i:0]

O14

O13

Figure 6-117. OSPI Timing Requirements – Tap DDR, No Loopback

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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