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TDA4VM21 Datasheet(PDF) 288 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 288 Page - Texas Instruments |
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288 / 331 page  Table 6-107. Timers Timing Conditions (continued) PARAMETER DESCRIPTION MODE MIN MAX UNIT OUTPUT CONDITIONS CL Output load capacitance PWM 2 10 pF Section 6.9.5.23.1, Section 6.9.5.23.2 and Figure 6-119 present timings and switching characteristics of the Timers. 6.9.5.23.1 Timing Requirements for Timers NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T1 tw(TINPH) Pulse duration, high CAPTURE 2.5 + 4P (1) ns T2 tw(TINPL) Pulse duration, low CAPTURE 2.5 + 4P (1) ns (1) P = functional clock period in ns. 6.9.5.23.2 Switching Characteristics for Timers NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T3 tw(TOUTH) Pulse duration, high PWM -2.5 + 4P (1) ns T4 tw(TOUTL) Pulse duration, low PWM -2.5 + 4P (1) ns (1) P = functional clock period in ns. T1 T2 TIMER_IOx (inputs) TIMER_01 T3 T4 TIMER_IOx (outputs) Figure 6-119. Timer Timing For more information, see Timers section in Peripherals chapter in the device TRM. 6.9.5.24 UART For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-108 represents UART timing conditions. Table 6-108. UART Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 30 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 www.ti.com 288 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VM-Q1 TDA4VM |
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