TDA4VM21 datasheet(287/331 Pages) TI

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Table 6-106. OSPI0/1 Switching Characteristics – Tap DDR Mode

see Figure 6-118

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0/1_CLK

tw(CLKL)

Pulse duration, OSPI0/1_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0/1_CLK high

((0.475P(1)) - 0.3)

td(CSn-CLK)

Delay time, OSPI0/1_CSn[3:0] active edge

to OSPI0/1_CLK rising edge

((0.475P(1)) +

((0.975M(2)R(5)) -

1.5)

((0.525P(1)) +

( 1.025M(2)R(5)) +

1.5)

td(CLK-CSn)

Delay time, OSPI0/1_CLK rising edge to

OSPI0/1_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(5)) - 1.5)

((0.525P(1)) +

(1.025N(3)R(5)) +

1.5)

td(CLK-D)

Delay time, OSPI0/1_CLK active edge to

OSPI0/1_D[7:0] transition

(–17.94 +

(0.975(T(4) + 1)R(5)))

(–1.56 +

(1.025(T(4) + 1)R(5)))

(1)

P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]

(5)

R = reference clock cycle time in ns

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 6-118. OSPI Switching Characteristics – Tap DDR, No Loopback

6.9.5.22 PCIE

The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the

specification for timing details.

For more details about features and additional description information on the device Peripheral Component

Interconnect Express, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7,

Detailed Description.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

6.9.5.23 Timers

For more details about features and additional description information on the device Timers, see the

corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.

Table 6-107 represents Timers timing conditions.

Table 6-107. Timers Timing Conditions

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

CAPTURE

0.5

V/ns

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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