TDA4VM21 datasheet(291/331 Pages) TI

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Table 6-111. JTAG Timing Conditions

PARAMETER

MIN

MAX

UNIT

Input Conditions

SRI

Input slew rate

0.25

2.00

V/ns

Output Conditions

Output load capacitance

6.9.6.2.1 JTAG Electrical Data and Timing

Section 6.9.6.2.1.1, Section 6.9.6.2.1.2, and Figure 6-122 assume testing over the recommended operating

conditions and electrical characteristic conditions.

6.9.6.2.1.1 JTAG Timing Requirements

See Figure 6-122

NO.

MIN

MAX UNIT

tc(TCK)

Cycle time minimum, TCK

100

tw(TCKH)

Pulse width minimum, TCK high

tw(TCKL)

Pulse width minimum, TCK low

tsu(TDI-TCK)

Input setup time minimum, TDI valid to TCK high

tsu(TMS-TCK)

Input setup time minimum, TMS valid to TCK high

th(TCK-TDI)

Input hold time minimum, TDI valid from TCK high

7.7

th(TCK-TMS)

Input hold time minimum, TMS valid from TCK high

7.7

1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in

this table only apply when the two IO power domains are operating at the same voltage. Values for these

timing parameters are not defined when operating the two IO power domains at different voltages since

propagation delay through the device IO buffers differ when some are operating at 1.8V while others are

operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG

interface is still expected to function when the two IO power domains are operated at different voltages,

assuming the system designer has implemented appropriate level shifters and the operating frequency is

reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different

voltages.

6.9.6.2.1.2 JTAG Switching Characteristics

See Figure 6-122

NO.

PARAMETER

MIN

MAX

UNIT

td(TCKL-TDOI)

Delay time minimum, TCK low to TDO invalid

td(TCKL-TDOV)

Delay time maximum, TCK low to TDO valid

37.75