TDA4VM21 datasheet(294/331 Pages) TI

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7.2 Processor Subsystems

7.2.1 Arm Cortex-A72

The device implements one dual-core Arm® Cortex®-A72 MPU, which is integrated inside the Compute Cluster,

along with other modules. The Cortex-A72 cores are general-purpose processors that can be used for running

customer applications.

The A72SS is built around the Arm Cortex-A72 MPCore (A72 cluster), which is provided by Arm and configured

by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high performance and

optimal power management and debug capabilities.

The A72 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 instruction and

data caches, compatible with Armv8-A architecture. The Armv8-A architecture brings a number of new features.

These include 64-bit data processing, extended virtual addressing and 64-bit general purpose registers.

For more information, see Dual-A72 MPU Subsystem section in Processors and Accelerators chapter in the

device TRM.

7.2.2 Arm Cortex-R5F

The MCU_ARMSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for split/lock

operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®

CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and

various wrappers for protocol conversion and address translation for easy integration into the SoC.

For more information, see Dual-R5F MCU Subsystem section in Processors and Accelerators chapter in the

device TRM.

7.2.3 DSP C71x

The TMS320C71x is the next-generation fixed and floating-point DSP platform. The C71x DSP is a new core in

the Texas Instruments' DSP family. The C71x DSP supports vector signal processing, providing significant lift in

DSP processing power over a broad range of general signal processing tasks in comparison to the C6x DSP

family. In addition, the C71x provides several specialized functions which accelerate targeted functions by more

than 30 times. Besides expanding vector processing capabilities, the new C71x core also incorporates advanced

techniques to improve control code efficiency and ease of programming such as branch prediction, protected

pipeline, precise exception and virtual memory management.

For more information, see C71x DSP Subsystem section in Processors and Accelerators chapter in the device

TRM.

7.2.4 DSP C66x

The C66x subsystem is based on the TI's standard TMS320C66x DSP CorePac module. It includes subsystem

logic to ease the C66x CorePac integration into the SoC, while maximizing software reuse from previous

devices.

The C66x DSP extends the performance of the C64x+ and C674x DSPs through enhancements and new

features. Many of the new features target increased performance for vector processing. The C64x+ and C674x

DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On C66x DSP,

the vector processing capability is improved by extending the width of the SIMD instructions.

The C66x DSP can execute instructions that operate on 128-bit vectors. For example, the QMPY32 instruction

is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The

C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each

instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000

architecture (for example, execution of up to eight instructions per cycle) results in a very high level of parallelism

that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.

For more information, see C66x DSP Subsystem section in Processors and Accelerators chapter in the device

TRM.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

294

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