SC416 datasheet(13/34 Pages) SEMTECH

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SC416

Applications Information (continued)

CIN

VOUT

PAD

VDDP

ILIM

BST

VIN

+5V

Figure 6

The following over-current equation can be used for both

RDSON or resistive sensing. For RDSON sensing, the

MOSFET RDSON rating is used for the value of RSENSE.

ILOC(Valley) = 10μA × RILIM / RSENSE

Power Good Output

Each output provides a power good (PGD) output, which

is an open-drain output requiring a pull-up resistor.

When the output voltage as sensed at FB is -9% from the

750mV reference (682mV), PGD is pulled low. It is held

low until the output voltage returns above -9% of nomi-

nal; the falling edge of VOUT does not latch PGD. PGD is

held low during start-up and will not be allowed to tran-

sition high until soft-start is completed, when SS reaches

750mV. There is a 5μsec delay built into the PGD circuit

to prevent false transitions.

PGD also transitions low if the FB pin exceeds +20% of

nominal (900mV), which is also the over-voltage shut-

down point.

Output Over-Voltage Protection (OVP)

When FB exceeds 20% of nominal (900mV), DL latches

high and the low-side MOSFET is turned on. DL stays high

and the output stays off until the EN/PSV input is toggled

or VDD is recycled. There is a 5μs delay built into the OVP

detector to prevent false transitions.

PGD is also held

low after an OVP.

Output Under-Voltage Protection (UVP)

When FB falls 30% below nominal (to 525mV) for eight

consecutive clock cycles, the output is shut off; the DL/

DH drives are pulled low to tri-state the MOSFETs, and

the converter stays off until its EN/PSV input is toggled

or the +5V supply at VDD1 supply is recycled. The other

output remains on during a UVP event.

POR and UVLO

Under-voltage lockout circuitry (UVLO) inhibits switch-

ing and tri-states all DH/DL drivers until the +5V supply at

VDD1 rises above 4.4V. An internal power-on reset (POR)

occurs when VDD1 exceeds 4.4V, which resets the fault

latches and quickly discharges the soft-start capacitors

to prepare the PWM for startup switching. At this time

the SC416 will exit UVLO and begin the startup cycle.

Startup Sequence

The startup sequence for each output relies on an exter-

nal ramp at the SS pin. During startup, the FB comparator

uses the SS ramp voltage as the reference until SS reach-

es 750mV, at which point the FB comparator switches

over to the internal 750mV reference. The external ramp

is typically created by connecting a capacitor to the SS

pin, which will be charged by a constant current. Or, the

SS pin can be connected to an external ramp provided

by the other output’s ramp-up as seen through a resistor

divider. See the Voltage Tracking section.

Before starting, with EN low, the SS pin is internally tied

to GND through 4kΩ. When EN is released, SS is briefly

pulled to GND through 16 ohms to discharge the SS ca-

pacitance. Then the resistances are removed, startup be-

gins, and a 5μA source current flows out of the SS pin.

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