AME, Inc.

21

AT7601F

Printer Port Controller

Rev. B.02

5-3-2.7 Interrupts

The interrupts are enabled by Servicelntr in the ECR register.

Servicelntr = 1 Disables the DMA and all of the service interrupts.

Servicelntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the

interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during

Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.

The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt

sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that

other interrupts may assert.

An interrupt is generated when:

1. For DMA transfers: When Servicelntr is 0, DMAEn is 1and the DMA TC is received.

2. For Programmed I/O:

a. When Servicelntr is 0, DMAEn is 0, direction is 0 and there are writeIntrThreshold or more free

bytes in the FIFO. Also, an interrupt is generated when Servicelntr is cleared to 0 whenever there

are writeIntrThreshold or more free bytes in the FIFO.

b. When Servicelntr is 0, DMAEn is 0, direction is 1 and there are readlntrThreshold or more bytes

in the FIFO. Also, an interrupt is generated when Servicelntr is cleared to 0 whenever

there are readlntrThreshold or more bytes in the FIFO

3. When ErrIntrEn# is 0 and Fault# transitions from high to low or when ErrIntrEn# is set from 1 to 0 and

ErrIntrEn# is set from 1 to 0 and Fault# is asserted.

4. When AckIntEn is 1 and the ACK# signal transitions from a low to a high.

5-3-2.8 FIFO Operation

The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port

can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO

is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be

addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Pro-

grammed I/O cycle or PDRQ depending on the selection of DMA or Programmed I/O mode.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>

ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to

15.

A low threshold value (i.e.2) results in longer periods of time between service requests, but requires faster

servicing of the request for both read and write cases. The host must be very responsive to the service

request. This is the desired case for use with a "fast" system.

A high value of threshold (i.e.2) is used with a "sluggish" system by affording a ling latency period after a

service request, but results in more frequent service requests.