AME, Inc.

13

AT7601F

Printer Port Controller

Rev. B.02

* Registers are in all modes.

** All FIFOs use one common 16-byte FIFO.

5-3-1.1 Data and ECP- AFIFO Port

ADDRESS OFFSET = 400H

Modes 000 and 001 (Data Port)

The Data Port is located at an offset of '00H'from the base address. The data register is cleared at

initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data

bus on the rising edge of the IOW# input. The contents of this register are buffered (non inverting) and

output onto the PD0-PD7 ports. During a READ operation, PD0-PD7 ports are read and output to the

host CPU.

Mode 011 (ECP FIFO-Address/RLE)

A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The

hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this

register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward

Timing Diagram, located in the Timing Diagrams section of this data sheet.

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ECP-AFIFO

Addr/RLE

**

DSR

BUSY#

ACK#

PError

SLCT

Fault#

1

1

1

*

DCR

1

1

PDIR

AckIntEn

SLIN

INIT#

AFD

STB

*

C-FIFO

**

ECP-DFIFO

**

T-FIFO

**

Cnfg-A

0

0

0

1

0

0

0

0

Cnfg-B

Compress

IntrValue

IRQ

IRQ

IRQ

DMA

DMA

DMA

ECR

ErrIntrEn#

DMA

En/Dis

Service

Intr

FIFO

Full

FIFO

EMPTY

MODE

Test FIFO

Address or RLE field

Table 10. Parallel Port and ECP Registers

Parallel Port Data FIFO

ECP Data FIFO