TMP89FS60 datasheet(163/410 Pages) TOSHIBA

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Page 149

TMP89FS60

RA001

13.4.1.4 Register buffer configuration

(1)

Temporary buffer

The TMP89FS60 contains an 8-bit temporary buffer. When a write instruction is executed on

TA0DRAL, the data is first stored into this temporary buffer, whether the double buffer is enabled or

disabled. Subsequently, when a write instruction is executed on TA0DRAH, the set value is stored

into the double buffer or TA0DRAH. At the same time, the set value in the temporary buffer is stored

into the double buffer or TA0DRAL. (This structure is designed to enable the set values of the lower-

level and higher-level registers simultaneously.) Therefore, when setting data to TA0DRA, be sure to

write the data into TA0DRAL and TA0DRAH in this order.

See Figure 13-1 for the temporary buffer configuration.

(2)

Double buffer

In the TMP89FS60, the double buffer can be used by setting TA0CR<TA0DBF>. Setting

TA0CR<TA0DBF> to "0" disables the double buffer. Setting TA0CR<TA0DBF> to "1" enables the

double buffer.

See Figure 13-1 for the double buffer configuration.

- When the double buffer is enabled

When a write instruction is executed on TA0DRAH during the timer operation, the set

value is first stored into the double buffer, and TA0DRAH/L are not updated immediately.

TA0DRAH/L compare the up counter value to the last set values. If the values are matched,

an INTTCA0 interrupt request is generated and the double buffer set value is stored in

TA0DRAH/L. Subsequently, the match detection is executed using a new set value.

When a read instruction is executed on TA0DRAH/L, the double buffer value (the last set

value) is read, rather than the TA0DRAH/L values (the current effective values).

When a write instruction is executed on TA0DRAH/L while the timer is stopped, the set

value is immediately stored into both the double buffer and TA0DRAH/L.

- When the double buffer is disabled

When a write instruction is executed on TA0DRAH during the timer operation, the set

value is immediately stored into TA0DRAH/L. Subsequently, the match detection is exe-

cuted using a new set value.

If the values set to TA0DRAH/L are smaller than the up counter value, the match detection

is executed using a new set value after the up counter overflows. Therefore, the interrupt

request interval may be longer than the selected time. If that is a problem, enable the double

buffer.

When a write instruction is executed on TA0DRAH/L while the timer is stopped, the set

value is immediately stored into TA0DRAH/L.

TMP89FS60 Datasheet(PDF) 163 Page - Toshiba Semiconductor