ADF4382ABCCZ datasheet(27/82 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. A | 27 of 82

Table 19. Double Buffer Enabled Bit Fields (Continued)

Double Buffer Enabled Bits

Double Buffered Bit Fields

DCLK_DIV_DB

DCLK_DIV1

DEL_CTRL_DB

INV_RFKOUT, BLEED_I, BLEED_POL

Serial Port

The SPI-compatible serial port provides control and monitoring

functionality. The CMOS_OV bit (Register 0x03D, Bit 5) determines

if the logic high level for the SDO and SDIO SPI output pins is 3.3

V or 1.8 V. The CMOS_OV bit also sets the output level for the

MUXOUT and LKDET pins.

The serial port can be programmed to support several different

configurations in Register 0x000 and Register 0x001.

The SDO_ACTIVE bit (Register 0x000, Bit 3) determines if the

serial port is configured as a 3-wire or 4-wire serial interface (see

the timing diagrams in Figure 2, Figure 3 and Figure 4).

Figure 51. Serial Interface, MSB First (LSB_FIRST = 0)

Figure 52. Serial Interface, LSB First (LSB_FIRST = 1)

The SPI register map can be programmed with single instructions,

as shown in Figure 51 and Figure 52, or in streaming mode.

Streaming mode allows for efficient data transfer read or write

cycles to multiple registers. Streaming mode allows the user to

program a bit stream composed of one register address in the

instruction header and data for that register address, which is then

followed by data in subsequent register addresses.

VCO

The VCO core consists of two separate VCOs both of which uses

512 overlapping bands, which allows the device to cover a wide

frequency range without large VCO tuning sensitivity (KVCO). The

output frequency can be further extended by utilizing the output

divider.

Figure 53. VCO and Clock Output Divider

The correct VCO core, band, and bias are chosen automatically by

performing a VCO calibration. After a VCO calibration is performed

for a specific frequency, the VCO core, band, and bias values

can be recorded for that particular device. These values can be

programmed manually later when the same device and frequency

are used, thereby avoiding the VCO calibration time.

VCO Calibration

A VCO calibration is required to select the correct VCO core, band,

and bias settings for a specific VCO frequency. This procedure

assumes that the device is powered up, the desired reference

frequency is present on the REFP and REFN pins, and all other

registers are programmed correctly. Figure 54 and Figure 55 are

provided as visual aids for this procedure.

Figure 54. VCO Calibration Dividers

ADF4382ABCCZ Datasheet(PDF) 27 Page - Analog Devices

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