ADF4382ABCCZ datasheet(34/82 Pages) AD

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Data Sheet

ADF4382A

APPLICATIONS INFORMATION

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Rev. A | 34 of 82

LOOP FILTER DESIGN

A stable loop filter design requires care in selecting the loop filter

components of the ADF4382A. It is recommended to download and

install ADIsimPLL for loop filter design and simulation. ADIsimPLL

has an integrated tutorial for first time users and a help manual for

more complex topics. There are also several ADIsimPLL training

videos available on the ADIsimPLL web page. After a loop filter

is designed and simulated, it is recommended to verify the new

loop filter using the ADF4382A evaluation hardware. A full loop filter

design tutorial is beyond the scope of this data sheet. However,

some best practices are shown in the following list. ADIsimPLL aids

in defining and simulating these parameters. Any significant change

to these items requires a new loop filter design.

A stable loop filter must meet the following criteria:

►

Loop filter phase margin > 45°

►

Loop filter bandwidth < fPFD ÷ 10

The desired loop filter bandwidth is determined by the following

features of the ADF4382A:

►

ICP

►

KVCO

►

PFD frequency

►

Reference input phase noise (see the Reference Phase Noise

section).

►

Trade-off between minimizing jitter or settling time

The VTUNE pin has an internal 54 pF capacitor to GND that must

be included in the loop filter design. ADIsimPLL takes this internal

capacitance into account automatically.

Another consideration when selecting the loop filter components is

the largest value capacitor in the loop filter design because this will

directly affect the minimum VTUNE precharge time before a VCO

calibration. The minimum precharge time is calculated as follows:

tPRECHARGE= C ×VI

(47)

where:

I is the VCO calibration generator current (6 mA).

C is the largest loop filter capacitance.

V is the nominal charge pump voltage.

For example, using a capacitance value of 10 nF and charge pump

voltage of 3.6 V results in the following:

tPRECHARGE= 10 nF ×3.6 V

6 mA

= 6 μs

Refer to the VCO Calibration section for programming the pre-

charge time dependent bit fields.

VCAL_ZERO

VCAL_ZERO is used to extend the lower limit of the loop filter

bandwidth. Within the loop filter, the capacitor that is connected

directly to the VTUNE pin of the device determines the value

VCAL_ZERO is set to as per Table 25.

Table 25. VCAL_ZERO Setting

CVTUNE

VCAL_ZERO

≤22 nF

>22 nF

LOOP FILTER LAYOUT CONSIDERATIONS

When designing the layout for the loop filter signal path on the

PCB, use the following design recommendations to optimize per-

formance and reduce potential spurious signals. Refer to the EV-

ADF4382ASD2Z PCB design files for an optimized example loop

filter layout footprint. The default loop filter on this board has been

designed for integer mode performance with FPFD = 250 MHz.

1. Place capacitors that are connected directly to the charge pump

or VTUNE signals as close as possible to the corresponding

device pin. This ensures that the ground signals are close to the

device ground.

2. Place charge pump power supply decoupling capacitors as

close as possible to the charge pump pin. Due to the limited

available layout space, the charge pump supply decoupling

capacitors can be placed on the underside of the evaluation

board.

3. Insert ground vias in the ground pads of shunt capacitors for

optimal ground connections.

4. Reduce loop filter path length to ensure that the loop filter

components are close to the device, with ground pads close to

device ground.

REFERENCE SOURCE CONSIDERATIONS

Reference Input Network

The reference input buffer of the ADF4382A shown in Figure 43

provides a flexible interface to either differential or single-ended

frequency sources. Figure 60 to Figure 65 show the recommended

interfaces for different reference signal types. All characteristic

impedance (Z0 ) signal traces are 50 Ω transmission lines.

Figure 60. Single-Ended 50 Ω Source (VREF < 2.6 V p-p)

ADF4382ABCCZ Datasheet(PDF) 34 Page - Analog Devices

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