ADF4382ABCCZ datasheet(30/82 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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and MOD2WORD (Register 0x1C, Bits[23:16]; Register 0x1B,

Bits[15:8]; and Register 0x1A, Bits[7:0]) bit field values that this

divider comprises together with the fixed modulus MOD1WORD

(225). See the Output Frequency section for the relationship

between N_INT, FRAC1WORD, MOD1WORD, FRAC2WORD,

MOD2WORD, RFOUT_DIV, together with R and D, and the fREF,

fPFD, fVCO and fOUT frequencies.

SYNC Monitor

A SYNC signal monitor is provided to detect the presence of a

SYNC signal and to check the setup and hold time of the SYNC

and reference. This is reported through the SYNC_OK status flag.

If the SYNC monitor detects a setup and hold time requirement

has not been met, then SYNC_OK = 0 after a read back, which

indicates a fault event. The SYNC_OK bit also shows 0 when the

SYNC output is disabled. When SYNC_OK shows 0 after a read

back, it continues to read back 0 until the SYNC monitor is reset

by setting RST_SYNC_MON = 1 then back to 0. Then SYNC_OK

continues to read back 1, assuming the timing is within the limits of

the SYNC monitor. PD_SYNC_MON = 1 disables the SYNC signal

monitor.

Phase Adjust

One of the following two methods can be used to perform a phase

adjustment of the RFOUT signals relative to their initial phase:

►

Bleed current mode

►

Σ-Δ mode

To enable bleed current mode, set DEL_MODE = 0. To enable Σ-Δ

mode, set DEL_MODE = 1.

Bleed Current Phase Adjustment

A small programmable constant charge pump current, known as

a bleed current, can be applied to the charge pump to adjust the

phase. Bleed current phase adjustment is used in integer mode.

Bleed current can also be applied in fractional mode to optimize

performance (see the Charge Pump Bleed Current Optimization

section for more details). The LSB step size depends on the

RFOUT frequency. PHASE_ADJ_POL determines the direction of

the phase adjustment. When PHASE_ADJ_POL = 0, the phase

value is decreased. When PHASE_ADJ_POL = 1, the phase value

is increased.

Ensure the following bit fields are programmed accordingly to

enable bleed current adjustment:

1. Set EN_BLEED = 1.

2. Set EN_PHASE_RESYNC = 1.

3. Set DEL_MODE = 0.

4. Use PHASE_ADJUSTMENT to determine the amount by which

the phase is adjusted as follows:

PHASE_ADJUSTMENT =

Phase in Degrees ×511

250 µA

×ICP × fPFD

360×RFOUT (45)

The maximum adjustment time that can achieved using the bleed

current method is tRFOUT.

The bleed current applied can be read back from DEL_CNT.

Σ-Δ Modulator Phase Adjustment

The Σ-Δ modulator can be used to adjust the phase of the RFOUT

signal by applying an offset value. The device must be used in

fractional mode to adjust the Σ-Δ modulator, which is the case

whether a fractional or integer frequency is used. Note that the

in-band figure of merit degrades by 2 dB as compared with using

integer mode. In addition, the maximum fPFD is then 250 MHz in

fractional mode, as compared to 625 MHz in integer mode.

An advantage of using fractional mode for adjusting the phase is

that the range is infinite, which means that each time a phase

adjust is performed, the phase increments by the value stored in

the PHASE_ADJUSTMENT bits (Register 0x033, Bits[7:0]) without

any limit to the number of times this can be done.

Ensure that the following bit fields are programmed accordingly to

enable Σ-Δ phase adjustment:

1. Set EN_PHASE_RESYNC = 1.

2. Set DEL_MODE = 1.

3. Use PHASE_ADJUSTMENT to determine the amount by which

the phase is adjusted for the Σ-Δ modulator as follows:

PHASE_ADJUSTMENT = Phase in Degrees

360

×212

(46)

PHASE_ADJ_POL selects the direction of adjustment.

PHASE_ADJ_POL = 0 is positive and PHASE_ADJ_POL = 1 is

negative. The PHASE_ADJUSTMENT value currently applied can

be read back from the CUM_PHASE_ADJ bits (Register 0x061,

Bits[7:0]). The maximum value is 8192 decimal. If this value is

exceeded, the value overflows and wraps around.

When the required phase offsets are known prior to initializing the

device, the PHASE_WORD bits can be used to program an initial

phase offset using the same PHASE_ADJUSTMENT formula in this

section.

Phase Adjust Pins

The ADF4382A has a 2-wire digital interface bus protocol that

allows external control of the phase. This bus consists of DELSTR

(Pin 29) and DELADJ (Pin 28). The signals are CMOS output

signals with 1.8 V logic. This interface can be used in both bleed

current and Σ-Δ mode phase adjustment. To enable the 2-wire

interface, set EN_AUTO_ALIGN = 1.

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