ADF4382ABCCZ datasheet(37/82 Pages) AD

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Data Sheet

ADF4382A

APPLICATIONS INFORMATION

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Rev. A | 37 of 82

b. Set the output driver mode of the channel to LVPECL or

CML and set the mute select of the channel to 0. e.g. set

c. Set the Pulse Generator Mode Selection to Continuous

Mode by setting register 0x005A to 0x07.

d. Send a reseed request to start the references by setting

Reseed request to 1 and then 0, by setting register 0x001 to

0x80 then setting to 0x00.

2. Set up each ADF4382A as follows:

a. Initialize the ADF4382A with the default initialization set-

tings.

b. Set TIMED_SYNC = 0.

c. Set EN_REF_RST = 1.

d. Set EN_PHASE_RESYNC = 1.

e. Set SYNC_SEL = 1.

3. Verify that both ADF4382A devices are locked.

4. Synchronize both ADF4382A RFOUT signals:

a. On an oscilloscope, first verify that both ADF4382A parts

are not synchronized.

b. Set SW_SYNC = 1 on each ADF4382A.

c. Set Pulse Generator Mode Selection to 0 to stop the refer-

ence on the HMC7044B (set register 0x005A to 0x00).

d. Set Pulse Generator Mode Selection to 7 on the

HMC7044B (set register 0x005A to 0x07).

e. Send a pulse request by setting register 0x0001 to 0x04

then 0x0 to restart the reference.

f. Set SW_SYNC = 0 on each ADF4382A.

5. On the oscilloscope, verify that the outputs from both

ADF4382A devices are synchronized (aside from cable mis-

match).

Figure 71. EZSync Configuration

Timed Synchronization Method

The timed synchronization method uses an external synchroniza-

tion signal to synchronize multiple ADF4382A devices, which is the

more traditional method for synchronization of devices. This method

requires an additional external signal from the clock distribution

device to provide the synchronization signal. Each synchronization

signal must be matched for accurate output phase matching. A

rising edge of the synchronization pulse on the SYNC pin of the

ADF4382A triggers the start of the synchronization process which

puts the device into a reset state. On the falling edge of the syn-

chronization pulse, the RFOUT signal phase on each ADF4382A is

then aligned to a known phase relative to the reference phase.

The following steps outline the procedure to perform a timed syn-

chronization with two ADF4382A devices in the configuration shown

in Figure 72.

1. Set up the HMC7044B as follows:

a. Set the channels used as a reference to the ADF4382A to

asynchronous mode. (e.g. set Register 0x00C8 to 0xF3 for

channel 0).

b. Set the divider ratio of the reference channels to 16 for a

reference frequency of 250MHz. (set Register 0x00C9 for

channel 0).

c. Set the channels used as a SYNC signal to the ADF4382A

to dynamic mode. (e.g set Register 0x00D2 to 0xFF).

d. Set the divider ratio of the SYNC channels to 8.

e. Set the SYSREF Timer (Register 0x005B/5C ) value of the

HMC7044B the same as the divider value of the SYNC

channels.

f. Set the Pulse Mode Selection to 'Pulse' (set Register

0x005A to 0x01).

g. Send a reseed request to start the references by setting the

reseed request to 1 and then 0, by setting register 0x001 to

0x80 then setting to 0x00.

2. Set up the ADF4382A as follows:

a. Set TIMED_SYNC (Register 0x01E, Bit 5) = 1.

b. Set EN_REF_RST (Register 0x01E, Bit 6) = 1.

c. Set EN_PHASE_RESYNC (Register 0x01E, Bit 7) = 1.

d. Set SYNC_SEL (Register 0x053, Bit 5) = 0.

e. Set R_DIV (Register 0x020, Bits[5:0]) = 4.

f. Set EN_DRCLK (Register 0x02D, Bit 6) = 1.

g. Verify that the ADF4382A devices are locked.

3. Synchronize both ADF4382A devices:

a. Verify that both ADF4382A outputs are not synchronized.

b. Send a pulse generator request to the HMC7044B by tog-

gling Register 0x01 data from 0x04 to 0x00.

c. Both outputs on both ADF4382A devices should now be

phase synchronized.

Figure 72. Timed Synchronization Configuration

PHASE SYNCHRONIZATION SETTINGS

To optimize phase noise and spurious performance on the

ADF4382A, there are a number of bit fields that must be program-

ADF4382ABCCZ Datasheet(PDF) 37 Page - Analog Devices

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