LM10506 datasheet(35/43 Pages) TI2

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LM10506

COUT

CIN

LOOP1

LOOP2

LM10506

www.ti.com

SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014

10 Power Supply Recommendations

The device is designed to operate from a fixed input voltage supply at 3.3 V or 5 V but will operate at input

voltages between 3 V to 5.5 V.

11 Layout

11.1 Layout Guidelines

11.1.1 PCB Layout Considerations

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

Schematic Of LM10506 Highlighting Layout Sensitive Nodes

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched

rapidly. The first loop starts from the CIN input capacitor, to the regulator SWx_VIN pin, to the regulator SW

pin, to the inductor then out to the output capacitor COUT and load. The second loop starts from the output

capacitor ground, to the regulator SWx_GND pins, to the inductor and then out to COUT and the load (see

above). To minimize both loop areas the input capacitor should be placed as close as possible to the VIN

pin. Grounding for both the input and output capacitors should consist of a small localized top side plane that

connects to PGND. The inductor should be placed as close as possible to the SW pin and output capacitor.

2. Minimize the copper area of the switch node. The SW pins should be directly connected with a trace that

runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible and

with a sufficient width. However, a trace that is wider than 100 mils will increase the copper area and cause

too much capacitive loading on the SW pin. The inductors should be placed as close as possible to the SW

pins to further minimize the copper area of the switch node.

3. Have a single point ground for all device analog grounds. The ground connections for the feedback

components should be connected together then routed to the GND pin of the device. This prevents any

switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding

can result in degraded load regulation or erratic switching behavior.

4. Minimize trace length to the FB pin. The feedback trace should be routed away from the SW pin and inductor

to avoid contaminating the feedback signal with switch noise.

5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or

output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure

feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide

the best output accuracy.

Outside 7x7 array 0.4 mm 34-bump DSBGA, with 24 peripheral and 6 inner vias = 30 individual signals

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