LM87 datasheet(3/45 Pages) TI2

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LM87

www.ti.com

SNAS034J – APRIL 2000 – REVISED MARCH 2013

PIN DESCRIPTIONS(1)

Number

Type

Description

Name(s)

Number

of Pins

This pin normally functions as a three-state input that controls the two LSBs of

the Serial Bus Address. When this pin is tied to VCC the two LSBs are 01.

When tied to Ground, the two LSBs are 10. If this pin is not connected, the two

LSBs are 00. This pin also functions as an output during NAND Tree tests

ADD/NTEST_OUT

Digital I/0

(board-level connectivity testing). To ensure proper NAND tree function, this

pin should not be tied directly to VCC or Ground. Instead, a series 5 kΩ resistor

should be used to allow the test output function to work. Refer to NAND TREE

TESTS on NAND Tree testing.

This pin functions as an open-drain interrupt output for temperature interrupts

THERM#

Digital I/O

only, or as an interrupt input for fan control. It has an on-chip 100 k

Ω pullup

resistor.

SMBData

Digital I/O

Serial Bus bidirectional Data. Open-drain output.

SMBCLK

Digital Input

Serial Bus Clock.

FAN1/AIN1-

Analog/Digital Programmable as analog inputs (0 to 2.5V) or digital Schmitt Trigger fan

5-6

FAN2/AIN2

Inputs

tachometer inputs.

An active high input from an external circuit which latches a Chassis Intrusion

event. This line can go high without any clamping action regardless of the

Digital I/O

powered state of the LM87. There is also an internal open-drain output on this

line, controlled by Bit 7 of the CI Clear Register (46h), to provide a minimum

20 ms pulse.

The system ground pin. Internally connected to all circuitry. The ground

reference for all analog inputs and the DAC output. This pin needs to be

GND

GROUND

connected to a low noise analog ground plane for optimum performance of the

DAC output.

V+ (+2.8 V to +3.8

+3.3 VV+ power. Bypass with the parallel combination of 10

μF (electrolytic or

POWER

tantalum) and 0.1

μF (ceramic) bypass capacitors.

Interrupt active low open-drain output. This output is enabled when Bit 1 in the

Configuration Register is set to 1. The default state is disabled. It has an on-

INT# /ALERT#

Digital Output

chip 100 k

Ω pullup resistor. Alternately used as an active low output to signal

SMBus Alert Response Protocol.

Analog

0 V to +2.5 V amplitude 8-bit DAC output. When forced high on power up by

DACOut/NTEST_IN

Output/Digital an external voltage the NAND Tree Test mode is enabled which provides

Input

board-level connectivity testing.

Master Reset, 5 mA driver (open-drain), active low output with a 20 ms

minimum pulse width. Available when enabled via Bit 4 in the Configuration

RESET#

Digital I/O

100 k

Ω pullup resistor.

Analog input for monitoring the cathode of the first external temperature

−

Analog Input

sensing diode.

Analog input for monitoring the anode of the first external temperature sensing

D1+

Analog Input

diode.

+12Vin

Analog Input

Analog input for monitoring +12 V.

+5Vin

Analog Input

Analog input for monitoring +5 V.

Digitally programmable analog input for monitoring Vccp2 (0 to 3.6 V input

Vccp2/D2

−

Analog Input

range) or the cathode of the second external temperature sensing diode.

Digitally programmable analog input for monitoring +2.5 V or the anode of the

+2.5Vin/D2+

Analog Input

second external temperature sensing diode.

Analog input (0 to 3.6 V input range) for monitoring Vccp1, the core voltage of

Vccp1

Analog Input

processore 1.

Digitally programmable dual function digital inputs. Can be programmed to

monitor the VID pins of the Pentium/PRO and Pentium II processors, that

VID4/IRQ4-

20-24

Digital Inputs

indicate the operating voltage of the processor, or as interrupt inputs. The

VID0/IRQ0

values are read in the VID/Fan Divisor Register and the VID4 Register. These

inputs have on-chip 100 k

Ω pullup resistors.

TOTAL PINS

(1)

# Indicates Active Low (“Not”)

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