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LM87 Datasheet(PDF) 32 Page - Texas Instruments |
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LM87 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 45 page  LM87 SNAS034J – APRIL 2000 – REVISED MARCH 2013 www.ti.com Interrupt Mask Register 1—Address 43h Power on default – <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +2.5Vin/D2+ Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 1 Vccp1 Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 2 Vcc Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 3 +5Vin Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 4 Int. Temp. Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 5 Ext. Temp. Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 6 FAN1/AIN1 Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 7 FAN2/AIN2 Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. Interrupt Mask Register 2—Address 44h Power on default – <7:0> = 0000 0000 binary Bit Name Read/Write Description 0 +12Vin Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 1 Vccp2 Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 2 Reserved Read/Write 3 Reserved Read/Write 4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 5 THERM# Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 6 D1 Fault Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. 7 D2 Fault Read/Write A one disables the corresponding interrupt status bit for INT# interrupt. Reserved Register —Address 45h Power on default – <7:0> = 00h. Read/Write for backwards compatibility. CI Clear Register—Address 46h Power on default – <7:0> = 0000 0000 binary Bit Name Read/Write Description 0-6 Reserved Read/Write 7 CI Clear Read/Write A one outputs a minimum 20 ms (minimum) active low pulse on the Chassis Intrusion pin. The register bit self clears after the pulse has been output. 32 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM87 |
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