HD3SS3220RNHT datasheet(21/48 Pages) TI2

21 / 48 page

6.6 Register Maps

Table 6-6. CSR Registers

OFFSET

RESET

SECTION

0x07 through 0x00

[0x00, 0x54, 0x55, 0x53, 0x42,

0x33, 0x32, 0x32]

Device Identification

Device Identification Register

0x08

0x00

Connection Status

Connection Status Register

0x09

0x20

Connection Status and Control

0x0A

0x00

General Control

General Control Register

0xA0

0x02

Device Revision

Device Revision Register

6.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42,

0x33, 0x32, 0x32]

Figure 6-4. Device Identification Register

DEVICE_ID

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-7. Device Identification Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

DEVICE_ID

0x00

For the HD3SS3220 device these fields return a string of ASCII

characters returning HD3SS3220 addresses:

0x07 - 0x00 = {0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32}

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HD3SS3220, HD3SS3220L

SLLSES1E – DECEMBER 2015 – REVISED JULY 2025

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