HD3SS3220RNHT datasheet(32/48 Pages) TI2

32 / 48 page

9 Layout

9.1 Layout Guidelines

9.1.1 Suggested PCB Stackups

TI recommends a PCB of at least six layers. Table 9-1 provides example PCB stackups.

Table 9-1. Example PCB Stackups

6-LAYER

8-LAYER

10-LAYER

SIGNAL

GROUND

SIGNAL(1)

SIGNAL

SIGNAL(1)

SIGNAL

SIGNAL(1)

POWER/GROUND(2)

POWER

SIGNAL

POWER/GROUND(2)

GROUND

SIGNAL(1)

SIGNAL

SIGNAL(1)

GROUND

SIGNAL

(1)

Route directly adjacent signal layers at a 90° offset to each other

(2)

Plane may be split depending on specific board considerations. Ensure that traces on adjacent planes do not cross splits.

9.1.2 High-Speed Signal Trace Length Matching

Match the etch lengths of the relevant differential pair traces of each interface. The etch length of the differential

pair groups do not need to match (that is, the length of the transmit pair does not need to match the length of the

receive pair). When matching the intrapair length of the high-speed signals, add serpentine routing to match the

lengths as close to the mismatched ends as possible. See Figure 9-1 for more details.

Length-Matching at Matched Ends

Length-Matching at Mismatched Ends

Figure 9-1. Length Matching

HD3SS3220, HD3SS3220L

SLLSES1E – DECEMBER 2015 – REVISED JULY 2025

www.ti.com

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