HD3SS3220RNHT datasheet(33/48 Pages) TI2

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9.1.3 Differential Signal Spacing

To minimize crosstalk in high-speed interface implementations, the spacing between the signal pairs must be

a minimum of 5 times the width of the trace. This spacing is referred to as the 5W rule. A PCB design with a

calculated trace width of 6mils requires a minimum of 30mils spacing between high-speed differential pairs. Also,

maintain a minimum keep-out area of 30mils to any other signal throughout the length of the trace. Where the

high-speed differential pairs abut a clock or a periodic signal, increase this keep-out to a minimum of 50mils to

ensure proper isolation. For examples of high-speed differential signal spacing, see Figure 9-2 and Figure 9-3.

General Keep-Out

High-Speed/Periodic Keep-Out

Inter-Pair Keep-Out

TXn/DATAx

RXn/DATAy

TXn/DATAx

RXn/DATAy

Figure 9-2. USB3/SATA/PCIe Differential Signal Spacing (mils)

General Keep-Out

High-Speed/Periodic Keep-Out

Figure 9-3. USB2 Differential Signal Spacing (mils)

9.1.4 High-Speed Differential Signal Rules

• Do not place probe or test points on any high-speed differential signal.

• Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power

regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.

• After BGA breakout, keep high-speed differential signals clear of the SoC because high current transients

produced during internal state transitions can be difficult to filter out.

• When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an

adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals.

• Ensure that high-speed differential signals are routed ≥ 90mils from the edge of the reference plane.

• Ensure that high-speed differential signals are routed at least 1.5W (calculated trace-width × 1.5) away from

voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are

voided.

• Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission

lines.

• Maximize differential pair-to-pair spacing when possible.

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HD3SS3220, HD3SS3220L

SLLSES1E – DECEMBER 2015 – REVISED JULY 2025

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HD3SS3220RNHT Datasheet(PDF) 33 Page - Texas Instruments