HD3SS3220RNHT datasheet(27/48 Pages) TI2

27 / 48 page

7.2.1 Design Requirements

For this design example, use the parameters shown in Table 7-1.

Table 7-1. Design Parameters, DRP Port

PARAMETER

EXAMPLE

COMMENTS

VDD5

5.25V

VDD5 is used to provide VCONN power to CC pins. Value of this supply should

be ≥ 5V to keep VCONN ≥ 4.75V.

System_VBUS

5.25V

VDD5 and System_VBUS can be shorted together; however careful

consideration is needed to maintain desired VBUS and VCONN for the Type-C

port.

I2C I/O Supply

3.3V

1.8V is also an option.

When using the 3.3V supply, the customer must ensure that the VDD5 is 3V

and above. Otherwise the I2C may back power the device

VCC33

3.3V

3-3.6V range allowed.

AC Coupling Capacitors for SS signals

100nF

75-200nF range allowed.

For TX pairs only, RX pairs will be biased by host Receiver. Note that

HD3SS3220 requires a common mode biasing of 0-2V. If host receiver has

bias voltage outside this range, appropriate additional ac coupling caps and

biasing of HD3SS3220 RX pairs needed.

Pull-up Resistors: DIR, ID, INT_N,

VCONN_FAULT_N

200K

Smaller values can be used, but leakage needs to be considered for device

power budget calculations.

Pull-up Resistors: I2C

4.7K

Pull-up Resistors: CURRENT_MODE

10K

Example here is for 3A. If 1.5A or 900mA needed different values are required.

Series resistor: VBUS_DET

900K

Decoupling Capacitors: VCONN Bulk

100μF

Decoupling Capacitors: VBUS Bulk

150μF

As indicated in schematic needs to be switched out when in UFP.

7.2.2 Detailed Design Procedure

HD3SS3220 can be used to design a USB Type-C DRP Port. In DRP mode the device alternate itself as DFP

and UFP according to USB-C specifications. An example schematic for DRP implementation is illustrated in

Figure 7-1.

www.ti.com

HD3SS3220, HD3SS3220L

SLLSES1E – DECEMBER 2015 – REVISED JULY 2025

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