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HD3SS3220RNHT Datasheet(PDF) 8 Page - Texas Instruments |
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HD3SS3220RNHT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 48 page ![]() over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL Differential return loss f = 0.3Mhz –27 dB f = 2.5Ghz –9 f = 5Ghz –9 OIRR Differential OFF isolation f = 0.3Mhz –79 dB f = 2.5Ghz –23 f = 5Ghz –20 XTALK Differential Cross Talk f = 0.3Mhz –89 dB f = 2.5Ghz –34 f = 5Ghz –30 RON On resistance 8 Ω (1) When using 3.3V for I2C, customer must ensure VDD5 is above 3V at all times. 5.6 Timing Requirements MIN NOM MAX UNIT I2C (SDA, SCL) tSU:DAT Data setup time 100 ns tHD:DAT Data setup time 10 ns tSU;STA Set-up time, SCL to start condition 0.6 µs tHD,STA Hold time,(repeated) start condition to SCL 0.6 µs tSU:STO Set up time for STOP condition 0.6 µs tVD;DAT Data valid time 0.9 µs tVD;ACK Data valid acknowledge time 0.9 µs tBUF Bus free time between a STOP and START condition 1.3 µs fSCL SCL clock frequency; I2C mode for local I2C control 400 ns tr Rise time of both SDA and SCL signals 300 ns tf Fall time of both SDA and SCL signals 300 ns CBUS_100KHZ Total capacitive load for each bus line when operating at ≤ 100KHz 400 pF CBUS_400KHZ Total capacitive load for each bus line when operating at 400KHz. 100 pF SS MUX tPD Switch propagation delay See Figure 5-3 80 ps tSW_ON Switching time DIR-to-Switch ON See Figure 5-2 0.5 µs tSW_OFF Switching time DIR-to-Switch OFF See Figure 5-2 0.5 µs tSK_INTRA Intra-pair output skew See Figure 5-3 5 ps tSK_INTER Inter-pair output skew See Figure 5-3 20 ps Power-On Timings tENnCC_HI ENn_CC high after both VDD5 and VCC33 supplies are stable. Refer to Figure 6-3. 2 ms tVDD5V_PG VDD5 stable before VCC33. Refer to Figure 6-2. 2 ms HD3SS3220, HD3SS3220L SLLSES1E – DECEMBER 2015 – REVISED JULY 2025 www.ti.com 8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: HD3SS3220 HD3SS3220L |
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