HD3SS3220RNHT datasheet(4/48 Pages) TI2

4 / 48 page

I/O

DESCRIPTION

NAME

NO.

TX1p

I/O

Type-C Port - USB SuperSpeed differential Signal TX1 positive

RX2n

I/O

Type-C Port - USB SuperSpeed differential Signal RX2 negative

RX2p

I/O

Type-C Port - USB SuperSpeed differential Signal RX2 positive

TX2n

I/O

Type-C Port - USB SuperSpeed differential Signal TX2 negative

TX2p

I/O

Type-C Port - USB SuperSpeed differential Signal TX2 positive

ADDR

Tri-level input pin to indicate I2C address or GPIO mode:

H (connect to VDD5) - I2C is enabled and I2C 7-bit address is 0x67.

NC - GPIO mode (I2C is disabled)

L (connect to GND) - I2C is enabled and I2C 7-bit address is 0x47.

ADDR pin should be pulled up to VDD5 if high configuration is desired

INT_N/OUT3

The INT_N/OUT3 is a dual-function pin.

When used as the INT_N, the pin is an open drain output in I2C control mode and is an active low

interrupt signal for indicating changes in I2C registers.

When used as OUT3, the pin is in audio accessory detect in GPIO mode:

H - no detection, and

L - audio accessory connection detected. For HD3SS3220L, OUT3 is a No Connect(NC) pin.

VCONN_FAULT_N

Open drain output. Asserted low when VCONN overcurrent detected.

SDA/OUT1

I/O

The SDA/OUT1 is a dual-function pin.

When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication data signal.

When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C

current mode detect when the device is in UFP mode:

H – Default (900 mA) current mode detected, and

L – Medium (1.5 A) or High (3 A) Current Mode detected.

SCL/OUT2

I/O

The SCL/OUT2 is a dual function pin.

When I2C is enabled (ADDR pin is high or low), this pin is the I2C communication clock signal.

When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating Type-C

current mode detect when the device is in UFP mode:

H – Default or Medium current mode detected, and

L – High current mode detected.

Open drain output. Asserted low when CC pin detected device attachment when port is a source

(DFP), or dual-role (DRP) acting as source (DFP).

ENn_CC

Enable signal for CC controller. Enable is active low.

VDD5

5V Power supply

Thermal Pad

–

The thermal PAD must be connected to GND, see the Thermal Pad connection techniques

(PowerPAD™ Thermally Enhanced Package application note).

HD3SS3220, HD3SS3220L

SLLSES1E – DECEMBER 2015 – REVISED JULY 2025

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