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HD3SS3220RNHT Datasheet(PDF) 39 Page - Texas Instruments

Part # HD3SS3220RNHT
Description  HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX
PDF  48 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

HD3SS3220RNHT Datasheet(HTML) 39 Page - Texas Instruments

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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 Trademarks
All trademarks are the property of their respective owners.
11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2020) to Revision E (July 2025)
Page
• Added additional HD3SS3220L device throughout the document..................................................................... 1
Changes from Revision C (May 2017) to Revision D (September 2020)
Page
• Changed VDD to VDD5......................................................................................................................................3
• In Control Pins row of Absolute Maximum Ratings, DIR was in both VDD5 and VCC33. Removed DIR
from VDD5..........................................................................................................................................................5
• Deleted C(bus,I2c) from the Recommended Operating Conditions table .............................................................5
• From: When using 3.3 V for I2C, customer must ensure VDD is above 3 V at all times. To: When using 3.3 V
for I2C, customer must ensure VDD5 is above 3 V at all times..........................................................................6
• Changed the "I2C (SDA, SCL)" section of the Timing Requirements table........................................................8
• Added tENnCC_HI parameter in section of the Timing Requirements table.......................................................... 8
• Added tVDD5V_PG parameter in section of the Timing Requirements table......................................................... 8
• Added note in section DFP/Source – Downstream Facing Port that ID pin will remain high until VBUS is
at VSafe0V........................................................................................................................................................14
• From: When a voltage level within the proper threshold is detected on CC1, the DIR pin is pulled low. To:
When a voltage level within the proper threshold is detected on CC1, the DIR pin is high..............................16
• From: When a voltage level within the proper threshold is detected on CC2, the DIR pin is high. To: When a
voltage level within the proper threshold is detected on CC2, the DIR pin is pulled low.................................. 16
• From: HD3SS3220 supports audio and debug accessories in UFP, DFP and DRP mode. To: HD3SS3220
supports audio and debug accessories in UFP, DFP and DRP mode by default............................................. 16
• Added note that UFP accessory support can be disabled by setting DISABLE_UFP_ACCESSORY register.16
• Added section on VDD5 and VCC33 power-on requirements..........................................................................18
• Removed the Note about non-failsafe pins from Dead Battery section as this information is in the VDD5 and
VCC33 Power-On Requirements section......................................................................................................... 19
Changes from Revision B (September 2016) to Revision C (May 2017)
Page
• Added RVBUS values: MIN = 855, TYP = 887, MAX = 920 KΩ ..........................................................................6
Changes from Revision A (August 2016) to Revision B (September 2016)
Page
• Changed pins CC1 and CC2 values From: MIN = –0.3 MAX = VDD5 +0.3 To: MIN –0.3 MAX = 6 in the
Absolute Maximum Ratings ...............................................................................................................................5
www.ti.com
HD3SS3220, HD3SS3220L
SLLSES1E – DECEMBER 2015 – REVISED JULY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: HD3SS3220 HD3SS3220L



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