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INA159 Datasheet(PDF) 19 Page - Texas Instruments |
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INA159 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 51 page ![]() R1 24.7 k RB VB +VS ±VS +VS ±VS +VS ±VS +VS ±VS +VS ±VS Super- NPN Super- NPN RG (External) +VS ±VS Overvoltage Protection Overvoltage Protection RB ±IN +IN REF OUT Q1 Q2 A1 A2 A3 +VS IB Cancellation IB Cancellation R2 24.7 k 50 k 50 k 50 k 50 k RG RG 19 INA826 www.ti.com SBOS562G – AUGUST 2011 – REVISED JUNE 2020 Product Folder Links: INA826 Submit Documentation Feedback Copyright © 2011–2020, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Inside the INA826 See the Functional Block Diagram section for a simplified representation of the INA826. A more detailed diagram, shown in Figure 58, provides additional insight into the INA826 operation. Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA. The differential input voltage is buffered by Q1 and Q2 and is impressed across RG, causing a signal current to flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the input signal and refers the output signal to the REF terminal. The equations shown in Figure 58 describe the output voltages of A1 and A2. The VBE and voltage drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages. Figure 58. INA826 Simplified Circuit Diagram |
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