LPC2460 datasheet(41/68 Pages) PHILIPS

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LPC2460_2

Preliminary data sheet

Rev. 02 — 1 February 2008

41 of 68

NXP Semiconductors

LPC2460

Fast communication chip

values, and/or altering the CPU clock divider value. This allows a trade-off of power versus

processing speed based on application requirements. In addition, Peripheral power

control allows shutting down the clocks to individual on-chip peripherals, allowing ﬁne

tuning of power consumption by eliminating all dynamic power use in any peripherals that

are not required for the application. Each of the peripherals has its own clock divider which

provides even better power control.

The LPC2460 also implements a separate power domain in order to allow turning off

power to the bulk of the device while maintaining operation of the RTC and a small SRAM,

referred to as the Battery RAM.

7.24.4.1

Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.24.4.2

Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The

processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Sleep mode and the logic levels of chip pins remain static. The

output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The

32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The CCLK and

USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or

certain speciﬁc interrupts that are able to function without clocks. Since all dynamic

operation of the chip is suspended, Sleep mode reduces chip power consumption to a

very low value.

On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the

code execution and peripherals activities will resume after 4 cycles expire. If the main

external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconﬁgure the PLL and clock dividers accordingly.

7.24.4.3

Power-down mode

Power-down mode does everything that Sleep mode does but also turns off the IRC

oscillator.

On the wake-up from Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60

µs to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. The customers need

to reconﬁgure the PLL and clock dividers accordingly after a wake-up from Power-down

mode.

7.24.4.4

Power domains

The LPC2460 provides two independent power domains that allow the bulk of the device

to have power removed while maintaining operation of the RTC and the Battery RAM.

LPC2460 Datasheet(PDF) 41 Page - NXP Semiconductors

LPC2460 Datasheet(HTML) 41 Page - NXP Semiconductors

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