LPC2460 datasheet(33/68 Pages) PHILIPS

33 / 68 page

LPC2460_2

Preliminary data sheet

Rev. 02 — 1 February 2008

33 of 68

NXP Semiconductors

LPC2460

Fast communication chip

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identiﬁers.

• Full CAN messages can generate interrupts.

7.12 10-bit ADC

The LPC2460 contains one ADC. It is a single 10-bit successive approximation ADC with

eight channels.

7.12.1 Features

• 10-bit successive approximation ADC

• Input multiplexing among 8 pins

• Power-down mode

• Measurement range 0 V to Vi(VREF)

• 10-bit conversion time

≥ 2.44 µs

• Burst conversion mode for single or multiple inputs

• Optional conversion on transition of input pin or Timer Match signal

• Individual result registers for each ADC channel to reduce interrupt overhead

7.13 10-bit DAC

The DAC allows the LPC2460 to generate a variable analog output. The maximum output

value of the DAC is Vi(VREF).

7.13.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

7.14 UARTs

The LPC2460 contains four UARTs. In addition to standard transmit and receive data

lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.14.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

LPC2460 Datasheet(PDF) 33 Page - NXP Semiconductors

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