LPC2460 datasheet(2/68 Pages) PHILIPS

2 / 68 page

LPC2460_2

Preliminary data sheet

Rev. 02 — 1 February 2008

2 of 68

NXP Semiconductors

LPC2460

Fast communication chip

I General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,

I2S, and SD/MMC interface as well as for memory-to-memory transfers.

I Serial Interfaces:

N Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

N USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and

associated DMA controller.

N Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

N CAN controller with two channels.

N SPI controller.

N Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA

controller.

N Three I2C-bus interfaces (one with open-drain and two with standard port pins).

N I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

I Other peripherals:

N SD/MMC memory card interface.

N 160 General purpose I/O pins with conﬁgurable pull-up/down resistors.

N 10-bit ADC with input multiplexing among 8 pins.

N 10-bit DAC.

N Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

N Two PWM/timer blocks with support for three-phase motor control. Each PWM has

an external count inputs.

N RTC with separate power domain, clock source can be the RTC oscillator or the

APB clock.

N 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

N WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

I Standard ARM test/debug interface for compatibility with existing tools.

I Emulation trace module supports real-time trace.

I Single 3.3 V power supply (3.0 V to 3.6 V).

I Three reduced power modes: idle, sleep, and power-down.

I Four external interrupt inputs conﬁgurable as edge/level sensitive. All pins on port 0

and port 2 can be used as edge sensitive interrupt sources.

I Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).

I Two independent power domains allow ﬁne tuning of power consumption based on

needed features.

I Each peripheral has its own clock divider for further power saving. These dividers help

reducing active power by 20 % to 30 %.

I Brownout detect with separate thresholds for interrupt and forced reset.

I On-chip power-on reset.

LPC2460 Datasheet(PDF) 2 Page - NXP Semiconductors

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