TMUX6213 datasheet(29/45 Pages) TI2

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9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1.

Table 9-1. Design Parameters

PARAMETERS

VALUES

Supply (VDD)

20 V

Supply (VSS)

- 10 V

Input / Output signal range

-10 V to 20 V (Rail-to-Rail)

Control logic thresholds

1.8 V compatible

9.2.2 Detailed Design Procedure

The application shown in Figure 10-1 demonstrates how the TMUX621x can be used in semiconductor

test equipment for high-precision, high-voltage, multi-channel measurement applications. The TMUX621x can

support 1.8-V logic signals on the control input, allowing the device to interface with low logic controls of

an FPGA or MCU. The TMUX621x can be operated without any external components except for the supply

decoupling capacitors. The select pins have an internal pull-down resistor to prevent floating input logic. All

inputs to the switch must fall within the recommend operating conditions of the TMUX621x including signal range

and continuous current. For this design with a positive supply of 20 V on VDD, and negative supply of -10 V on

VSS, the signal range can be 20 V to -10 V. The max continuous current (IDC) can be up to 330 mA as shown in

the Recommended Operating Conditions table for wide-range current measurement.

9.2.3 Application Curve

The TMUX621x devices have excellent charge injection performance and low leakage current, making them

ideal choices to minimize sampling error for the sample and hold application.

Source Voltage (V)

-20

-15

-10

-5

-50

-30

-10

110

130

150

170

D016

VDD = 15 V, V SS = –15 V

VDD = 5 V, V SS = –5 V

TA = 25°C

Figure 9-2. Charge Injection vs Source Voltage

Temperature (

°C)

-40

-25

-10

110 125

-15

-12

-9

-6

-3

ID(OFF) VS/VD = –10V/10V

ID(OFF) VS/VD = 10V/–10V

I(ON) Vs/Vd = –10V/–10V

I(ON) Vs/Vd = 10V/10V

IS(OFF) Vs/Vd = –10V/10V

IS(OFF) Vs/Vd = 10V/–10V

VDD = 15 V, VDD = -15 V

Figure 9-3. On-Leakage vs Source or Drain Voltage

9.3 Power Supply Recommendations

The TMUX621x devices operates across a wide supply range of of ±4.5 V to ±18V (4.5 V to 36V in single-supply

mode). The devices also perform well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply

rails to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD

and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible

using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that

offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling

purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias

for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias

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TMUX6211, TMUX6212, TMUX6213

SCDS431D – OCTOBER 2020 – REVISED JULY 2024

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