TPA2016D2 datasheet(32/51 Pages) TI2

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TPA2016D2

SLOS524E – JUNE 2008 – REVISED MAY 2016

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10.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 12.

10.2.2.2 Detailed Design Procedure

For the design procedure see Detailed Design Procedure.

10.2.2.3 Application Curves

For application curves, see the figures listed in Table 14.

11 Power Supply Recommendations

The TPA2016D2 is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. Therefore

the output voltage range of the power supply must be within this range. The current capability of upper power

must not exceed the maximum current limit of the power switch.

11.1 Power Supply Decoupling Capacitors

The TPA2016D2 requires adequate power supply decoupling to ensure a high efficiency operation with low total

harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,

within 2 mm of the VDD/VCCOUT pin. This choice of capacitor and placement helps with higher frequency

transients, spikes, or digital hash on the line. In addition to the 0.1-

μF ceramic capacitor, is recommended to

place a 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir,

providing energy faster than the board supply, thus helping to prevent any droop in the supply voltage.

12 Layout

12.1 Layout Guidelines

12.1.1 Component Location

Place all the external components very close to the TPA2016D2. Placing the decoupling capacitor, CS, close to

the TPA2016D2 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace

between the device and the capacitor can cause a loss in efficiency.

12.1.2 Trace Width

Recommended trace width at the solder balls is 75

μm to 100 μm to prevent solder wicking onto wider PCB

traces. For high current pins (PVDD (L, R), PGND, and audio output pins) of the TPA2016D2, use 100-

μm trace

widths at the solder balls and at least 500-

μm PCB traces to ensure proper performance and output power for

the device. For the remaining signals of the TPA2016D2, use 75-

μm to 100-μm trace widths at the solder balls.

The audio input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation.

12.1.3 Pad Side

In making the pad size for the DSBGA balls, TI recommends that the layout use non solder mask defined

(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the

opening size is defined by the copper pad width. Figure 45 and Table 15 shows the appropriate diameters for a

DSBGA layout. The TPA2016D2 evaluation module (EVM) layout is shown in the next section as a layout

example.

TPA2016D2 Datasheet(PDF) 32 Page - Texas Instruments

TPA2016D2 Datasheet(HTML) 32 Page - Texas Instruments

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