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TPA2016D2 Datasheet(PDF) 33 Page - Texas Instruments |
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TPA2016D2 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 51 page ![]() 33 TPA2016D2 www.ti.com SLOS524E – JUNE 2008 – REVISED MAY 2016 Product Folder Links: TPA2016D2 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Layout Guidelines (continued) (1) Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. (2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. (3) Recommend solder paste is Type 3 or Type 4. (4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance. (5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern (6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. (7) Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. Table 15. Land Pattern Dimensions(1)(2)(3)(4) SOLDER PAD DEFINITIONS COPPER PAD SOLDER MASK(5) OPENING COPPER THICKNESS STENCIL(6)(7) OPENING STENCIL THICKNESS Non solder mask defined (NSMD) 275 μm (+0.0, –25 μm) 375 μm (+0.0, –25 μm) 1 oz max (32 μm) 275 μm × 275 μm Sq. (rounded corners) 125 μm thick Figure 45. Land Pattern Dimensions |
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