LM5145 datasheet(47/60 Pages) TI2

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7.4.2 Layout Example

Figure 7-23 shows a single-sided layout of a synchronous buck regulator with discrete power MOSFETs, Q1 and

Q2, in SON 5mm × 6mm case size. The power stage is surrounded by a GND pad geometry to connect an

EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the

top layer to create a low-area switching power loop of approximately 2mm². This loop area, and hence parasitic

inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.

The high-frequency power loop current flows through MOSFETs Q1 and Q2, through the power ground plane

on layer 2, and back to VIN through the 0402 ceramic capacitors C14 through C19. The currents flowing in

opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance.

Figure 7-25 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a

multilayer PCB structure. The layer 2 GND plane layer, shown in Figure 7-24, provides a tightly-coupled current

return path directly under the MOSFETs to the source terminals of Q2.

Six 10nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain of

Q1. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint

capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected

to the layer-2 GND plane with multiple 12mil (0.3mm) diameter vias, further minimizing parasitic loop inductance.

Inductor

VIN

VOUT

GND

Input Caps

PGND

VCC

AGND

VIN

GND

Copper island

connected to AGND

Output Caps

Locate controller close to the

power stage

Shunt

Use paralleled 0402/0603 input

capacitors close to the FETs for VIN

to PGND decoupling

Low-side

FET

High-side

FET

Place PGND vias close to the

source of the low-side FET

Optional shield

GND connection

Use PGND cut-out to

minimize eddy currents

DCR Sense

Figure 7-23. PCB Top Layer – High Density, Single-sided Design

Additional guidelines to improve noise immunity and reduce EMI are as follows:

www.ti.com

LM25139

SLVSJ80 – OCTOBER 2025

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