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ADC34RF72 Datasheet(PDF) 26 Page - Texas Instruments |
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ADC34RF72 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 74 page  7.3.5 Digital Signal Processor (DSP) Features The device includes several different digital features in the digital signal processing block: • 12-bit fractional delay with one sampling clock cycle range and a delay step size equal to 1/(212* tCLK) • Programmable FIR filter for equalization with up to 96-taps per channel • Multiple digital down converters (DDCs) supporting decimation factors of /2, /3 and /5 up to /32768 • Additional programmable FIR filter for equalization post decimation DDC0 FRACT. DELAY MUX & AVG (2x) EQ FIR MUX & AVG (2x) DDC /2K DDC /2,/3,/5 EQFIR GAIN NCO1 NCO0 MUX JESD 8 Lanes ADC0 ADC1 ADC3 ADC2 Figure 7-11. Digital signal processing chain ADC32RF72 SBASAL2 – NOVEMBER 2025 www.ti.com 26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: ADC32RF72 |
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