ADC34RF72 datasheet(47/74 Pages) TI2

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Table 7-18. JESD TX Link Registers (x: 0 = LINK0, 1 = LINK1) (continued)

System Parameter Name

Size

Default

Reset

Description

JESD_PHY_LANE{y}_DATA_SEL

0,1

Set the physical lane data source for the lane{y}. (y = 0..7).

0: JESD logical lane 0 used as the lane data.

1: JESD logical lane 1 used as the lane data.

2: JESD logical lane 2 used as the lane data.

3: JESD logical lane 3 used as the lane data.

4: JESD logical lane 4 used as the lane data.

5: JESD logical lane 5 used as the lane data.

6: JESD logical lane 6 used as the lane data.

7: JESD logical lane 7 used as the lane data.

JESD_PHY_LANE_POLARITY_CTRL

Set the individual physical lane polarity. If the bit is set, the corresponding

physical lane polarity is inverted.

Bit 0: JESD physical lane 0 polarity control.

Bit 1: JESD physical lane 1 polarity control.

Bit 2: JESD physical lane 2 polarity control.

Bit 3: JESD physical lane 3 polarity control.

Bit 4: JESD physical lane 4 polarity control.

Bit 5: JESD physical lane 5 polarity control.

Bit 6: JESD physical lane 6 polarity control.

Bit 7: JESD physical lane 7 polarity control.

7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNC signal. When a logic

low state is detected on the SYNC input, the ADC starts transmitting comma characters (K28.5) to establish

the code group synchronization, as shown in Figure 7-35. When synchronization is completed, the receiving

device reasserts the SYNC signal and the ADC starts the initial lane alignment sequence with the next local

multi-frame clock (LMFC) boundary. The ADC transmits four multi-frames, each containing K frame (K is SPI

programmable). Each of the multi-frames contains the frame start and frame end symbols. The second multi-

frame also contains the JESD204B link configuration data.

SYNC

SYSREF

LMFC Clock

LMFC Boundary

xxx

Transmit Data

K28.5

ILA

DATA

Multi-Frame

Code Group Synchronization

Initial Lane Alignment

Data Transmission

Figure 7-35. JESD204B Internal Timing Diagram

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ADC32RF72

SBASAL2 – NOVEMBER 2025

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