ADC34RF72 datasheet(46/74 Pages) TI2

46 / 74 page

Table 7-18. JESD TX Link Registers (x: 0 = LINK0, 1 = LINK1) (continued)

System Parameter Name

Size

Default

Reset

Description

LINK{x}_JESD_LANES

Set the JESD lanes (L) parameter for the link.

0: LINK is disabled.

1: JESD L parameter set to 1.

2: JESD L parameter set to 2.

4: JESD L parameter set to 4.

8: JESD L parameter set to 8.

LINK{x}_JESD_CONVERTERS

Set the JESD converters (M) parameter for the link.

0: LINK is disabled.

1: JESD M parameter set to 1.

2: JESD M parameter set to 2.

4: JESD M parameter set to 4.

8: JESD M parameter set to 8.

LINK{x}_JESD_OCTETS_PER_FRAME

Set the JESD octets per frame (F) parameter for the link. The max value is for

F is 64. If N' is 32 then F must be a multiple of 4.

1...64: JESD F parameter value.

LINK{x}_JESD_SAMPLES_PER_CONVER

TER

Set the JESD samples per converter (S) parameter for the link.

1: JESD S parameter set to 1.

2: JESD S parameter set to 2.

4: JESD S parameter set to 4.

LINK{x}_JESD_K_OR_E

Set either the JESD frames per multi-frame (K) or the multi-blocks per

extended multi-block (E). This field is the K parameter when 8b10b encoding is

used or E when 64b66b encoding is used.

LINK{x}_CONV_SEL_{y}

Select the data source of the {y} converter in the link. (y=0..7)

0: DDC0 in-phase component data.

1: DDC0 quadrature component data.

2: DDC1 in-phase component data.

3: DDC1 quadrature component data.

4: DDC2 in-phase component data.

5: DDC2 quadrature component data.

6: DDC3 in-phase component data.

7: DDC3 quadrature component data.

8: DDC4 in-phase component data.

9: DDC4 quadrature component data.

10: DDC5 in-phase component data.

11: DDC5 quadrature component data.

12: DDC6 in-phase component data.

13: DDC6 quadrature component data.

14: DDC7 in-phase component data.

15: DDC7 quadrature component data.

16: ADC0 data from DSP_OUT.

17: ADC1 data from DSP_OUT.

18: ADC2 data from DSP_OUT.

19: ADC3 data from DSP_OUT.

JESD_SYNC_N_SRC_SEL

Set the SYNC_N signal source for 8b10b.

0: GPIO0 used as SYNC_N input.

2: SYNC_N is internally generated through software.

ADC32RF72

SBASAL2 – NOVEMBER 2025

www.ti.com

Submit Document Feedback

Product Folder Links: ADC32RF72

ADC34RF72 Datasheet(PDF) 46 Page - Texas Instruments

ADC34RF72 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL