ADC34RF72 datasheet(28/74 Pages) TI2

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7.3.5.2 Fractional Delay

The device includes an optional programmable 12-bit fractional digital delay after the DSP input mux (see Figure

7-13). There are two independent digital fractional delay blocks - FDF0 and FDF1. Each FDF block is connected

to two input streams (dsp_in[1:0] or dsp_in[3:2]) where each input stream has a programmable fractional delay

value, td00 and td01 for dsp_in[1:0] and td10 and td11 for dsp_in[3:2]. The FDF blocks output a total of four data

streams (fdf_out[3:0]) where each output stream corresponds to a distinct fractionally delayed input stream.

The fractional delay is a true time delay implementation with a linear phase across frequencies. The fractional

delay calculates to:

Fractional Delay [sampling clock period] = Delay / 4096x TS (sampling period).

dsp_in[0]

td00

dsp_in[1]

td01

dsp_in[2]

td10

dsp_in[3]

td11

FDF0

FDF1

fdf_out[1:0]

DSP

MUX

fdf_out[3:2]

Figure 7-13. Fractional Delay Feature

As an example, a setting of 2048 equals ½ a clock cycle delay as shown in Figure 7-14. The magnitude error is

less than −80dB (vs desired delay).

Sample

-1

-0.5

0.5

1.5

Input Signal

Actual output

Figure 7-14. Fractional delay = ½ clock cycle

(delay setting = 2048)

Sample Index

-0.001

-0.0008

-0.0006

-0.0004

-0.0002

0.0002

0.0004

0.0006

0.0008

0.001

Figure 7-15. Error magnitude

(desired vs actual waveform)

ADC32RF72

SBASAL2 – NOVEMBER 2025

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