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ADC34RF72 Datasheet(PDF) 11 Page - Texas Instruments

Part # ADC34RF72
Description  ADC32RF72 Dual Channel 1.5GSPS 16-bit RF Sampling ADC
PDF  74 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADC34RF72 Datasheet(HTML) 11 Page - Texas Instruments

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5.8 Timing Requirements
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, DDC Bypass mode, 50% clock duty cycle,
nominal supply voltages and –1-dBFS differential input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ADC Timing Specifications
TAD
Aperture Delay
0.15
ns
Aperture Delay variation
0.05
ns
TA
Aperture Jitter
40
fs
CER
Code error rate
1e-15
errors/
sample
Wake up time
time to valid data (SNR within 2dB of data
sheet values) after coming out of fast power
down (JESD stays active)
5
μs
LATENCY: tPD + tADC
tPD
Propagation delay
1
ns
tADC
ADC latency from sampling instant to JESD
output
DDC bypass, LMFS = 8411
524
ADC
clock
cycles
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency
1
50
MHz
tS(SEN)
SEN to rising edge of SCLK
10
ns
tH(SEN)
SEN from rising edge of SCLK
10
ns
tSU(SDIO)
SDIO to rising edge of SCLK
10
ns
tH(SDIO)
SDIO from rising edge of SCLK
10
ns
SERIAL PROGRAMMING INTERFACE (SDIO, SDOUT) - Output
t(OZD)
SDIO tri-state to driven
10
ns
t(ODZ)
SDIO data to tri-state
14
ns
t(OD)
SDIO valid from falling edge of SCLK
10
ns
Timing: SYSREFP/N
ts(SYSREF)
Setup time, SYSREFP/N valid to rising edge
of CLKP/N
50
ps
th(SYSREF)
Hold time, SYSREFP/N valid to rising edge of
CLKP/N
50
ps
CML SerDes Outputs: STX[0..7]P/N
fSerdes
SerDes bit rate
4.0
24.75
Gbps
RJ
Random jitter
0.45
ps
DJ
Deterministic jitter
12.5
ps
TJ
Total jitter, peak-peak
19.7
ps
www.ti.com
ADC32RF72
SBASAL2 – NOVEMBER 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: ADC32RF72



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