TUSB1146 datasheet(24/68 Pages) TI2

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TUSB1146

SLLSFB2 – APRIL 2020

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8.3 Feature Description

8.3.1 USB 3.1

The TUSB1146 supports USB 3.1 Gen1/Gen2 datarates up to 10 Gbps. The TUSB1146 supports all the USB

defined power states (U0, U1, U2, and U3). Because the TUSB1146 is a linear redriver, it can’t decode USB3.1

physical layer traffic. The TUSB1146 monitors the actual physical layer conditions like receiver termination,

electrical idle, LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB 3.1 interface.

The TUSB1146 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector

automatically senses the low frequency signals and disables receiver equalization functionality. When not

receiving LFPS, the TUSB1146 will enable receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins or

values programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.

8.3.2 DisplayPort

The TUSB1146 supports up to 4 DisplayPort lanes at datarates up to 10 Gbps (UHBR10). The TUSB1146, when

configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and

DisplayPort sink. For the purposes of reducing power, the TUSB1146 manages the number of active DisplayPort

lanes based on the content of the AUX transactions. The TUSB1146 snoops native AUX writes to DisplayPort

sink’s DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE). TUSB1146

disables/enables lanes based on value written to LANE_COUNT_SET. The TUSB1146 disables all lanes when

SET_POWER_STATE is in the D3. Otherwise active lanes will be based on value of LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE

various configuration registers. When TUSB1146 is enabled for GPIO mode (I2C_EN = "0"), the CAD_SNK pin

can be used to disable AUX snooping. When CAD_SNK pin is high, the AUX snooping functionality is disabled

and all four DisplayPort lanes will be active.

8.3.3 4-level Inputs

The TUSB1146 has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to control

the equalization gain and place TUSB1146 into different modes of operation. These 4-level inputs utilize a

resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal

pull-up and pull-down resistors. These resistors, together with the external resistor connection combine to

achieve the desired voltage level.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTINGS

Option 1: Tie 1 K

Ω 5% to GND.

Option 2: Tie directly to GND.

Tie 20 K

Ω 5% to GND.

Float (leave pin open)

Option 1: Tie 1 K

Ω 5%to VCC.

Option 2: Tie directly to VCC.

NOTE

All four-level inputs are latched after rising edge of the internal reset. After tcfg_hd, the

internal pull-up and pull-down resistors will be isolated in order to save power.

8.3.4 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in

the system before the input of the TUSB1146. The receiver overcomes these losses by attenuating the low

frequency components of the signals with respect to the high frequency components. The proper gain setting

should be selected to match the channel insertion loss before the input of the TUSB1146 receivers. Two 4-level

inputs pins enable up to 16 possible equalization settings. USB3.1 upstream path, USB3.1 downstream path,

and DisplayPort each have their own two 4-level inputs. The TUSB1146 also provides the flexibility of adjusting

settings through I2C registers.

TUSB1146 Datasheet(PDF) 24 Page - Texas Instruments

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