TUSB1146 datasheet(37/68 Pages) TI2

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Slave Address

Write

Ack

Start

Stop

TUSB1146

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address and a one-value “W/R” bit to indicate a read cycle.

7. The TUSB1146 acknowledges the 7-bit address cycle.

8. The TUSB1146 transmit the contents of the memory registers MSB-first starting at the register offset.

9. The TUSB1146 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master

after each byte transfer; the I2C master acknowledges reception of each data byte transfer.

10. If an ACK is received, the TUSB1146 transmits the next byte of data as long as master provides the clock. If

a NAK is received, the TUSB1146 stops providing data and waits for a stop condition (P).

11. The master terminates the read operation by generating a stop condition (P).

Figure 32. I2C Write without data

The following procedure should be followed for setting a starting sub-address for I2C reads (refer to Figure 32).

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB1146 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB1146 acknowledges the address cycle.

3. The master presents the register offset within TUSB1146 to be written, consisting of one byte of data, MSB-

first.

4. The TUSB1146 acknowledges the register offset cycle.

5. The master terminates the write operation by generating a stop condition (P).

NOTE

After initial power-up, if no register offset is included for the read procedure (refer to

Figure 30), then reads start at register offset 00h and continue byte by byte through the

registers until the I2C master terminates the read operation. During a read operation, the

TUSB1146 auto-increments the I2C internal register address of the last byte transferred

independent of whether or not an ACK was received from the I2C master.

TUSB1146 Datasheet(PDF) 37 Page - Texas Instruments