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TUSB1146 Datasheet(PDF) 40 Page - Texas Instruments |
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TUSB1146 Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 68 page  40 TUSB1146 SLLSFB2 – APRIL 2020 www.ti.com Product Folder Links: TUSB1146 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Table 14. DCI_TXEQ_CTRL Register Field Descriptions (continued) Bit Field Type Reset Description 4-3 TX_DEEPHASIS R/W 0x1 SSRX TX de-emphasis level (post-cursor) 0x0 = -1.5dB 0x1 = -2.1dB 0x2 = -3.2dB 0x3 = -3.8dB 2 TX_DEEPHASIS_EN R/W 0x1 SSRX TX de-emphasis (post-cursor) enable. Valid only when SSRX_LIMIT_ENABLE = 1. 0x0 = Disabled (0dB) 0x1 = Enabled 1-0 DCI_CTL R/W 0x0 Controls whether or not DCI function is enabled by FSM or software. 0x0 = DCI controlled by FSM 0x1 = DCI enabled using RX1P/N 0x2 = DCI enabled using RX2P/N 0x3 = DCI disabled. 8.6.1.3 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0] DP01EQ_SEL is shown in Table 15. Return to the Summary Table. This register controls the receiver equalization setting for the DisplayPort receivers 0 and 1. Table 15. DP01EQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 DP1EQ_SEL RH/W 0x0 Field selects EQ for DP lane 1 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 1 based on value written to this field. 3-0 DP0EQ_SEL RH/W 0x0 Field selects EQ for DP lane 0 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 0 based on value written to this field. 8.6.1.4 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0] DP23EQ_SEL is shown in Table 16. Return to the Summary Table. This register controls the receiver equalization setting for the DisplayPort receivers 2 and 3. Table 16. DP23EQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 DP3EQ_SEL RH/W 0x0 Field selects EQ for DP lane 3 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 3 based on value written to this field. 3-0 DP2EQ_SEL RH/W 0x0 Field selects EQ for DP lane 2 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 2 based on value written to this field. |
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