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TUSB1146 Datasheet(PDF) 11 Page - Texas Instruments |
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TUSB1146 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 68 page  11 TUSB1146 www.ti.com SLLSFB2 – APRIL 2020 Product Folder Links: TUSB1146 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 6.8 DCI Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DCI_CLK and DCI_DAT LVCMOS Outputs VOL Low-Level output voltage VCC = 3 V; IOL = 2 mA; CL = 10 pF 0.45 V VOH High-Level output voltage VCC = 3 V; IOL = –2 mA; 2.4 V RDCI Output characteristic impedance 21 25 33 Ω tPERIOD DCI Clock period Measured at 50% 7.52 ns tVALID Rising edge of DCI clock to DCI data valid 1 ns tDCI_RISE DCI output rise time Measured at 20% to 80%. 350 ps tDCI_FALL DCI output fall time Measured at 80% to 20% 350 ps (1) Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0]. (2) Recommend CFG pins are stable when VCC is at min. 6.9 Timing Requirements MIN NOM MAX UNIT USB3.1 tIDLEEntry Delay from U0 to electrical idle Refer to Figure 20. 10 ns tIDELExit_U1 U1 exist time: break in electrical idle to the transmission of LFPS Refer to Figure 20. 6 ns tIDLEExit_U2U3 U2/U3 exit time: break in electrical idle to transmission of LFPS Refer to Figure 20. 10 µs tRXDET_INTVL RX detect interval while in Disconnect 12 ms tIDLEExit_DISC Disconnect Exit Time 10 µs tExit_SHTDN Shutdown Exit Time 1 ms tAEQ_FULL_DONE Maximum time to obtain optimum EQ setting when operating in Full AEQ mode. 300 µs tAEQ_FAST_DONE Maximum time to determine appropriate EQ setting when operating in Fast AEQ mode. 60 µs tDIFF_DLY Differential Propagation Delay Refer to Figure 19. 300 ps tR, tF Output Rise/Fall time 20%-80% of differential voltage measured 1.7 inch from the output pin; Refer to Figure 21. 40 ps tRF_MM Output Rise/Fall time mismatch 20%-80% of differential voltage measured 1.7 inch from the output pin 2.6 ps Power-up tD_PG VCC(min) to internal Power Good asserted high Refer to Figure 27 25 ms tCFG_SU CFG(1) pins setup(2) Refer to Figure 27 250 µs tCFG_HD CFG(1) pins hold Refer to Figure 27 10 µs tCTL_DB CTL[1:0] and FLIP pin debounce Refer to Figure 27 16 ms 6.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUXp or AUXn and SBU1 or SBU2 tAUX_PD Switch propagation delay 400 ps tAUX_SW_OFF Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. Refer to Figure 23. 500 ns tAUX_SW_ON Switching time CTL1 to switch ON Refer to Figure 22. 500 ns tAUX_INTRA Intra-pair output skew 100 ps USB3.1 and DisplayPort Mode Transition Requirement GPIO Mode tGP_USB_4DP Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa. I2C_EN = 0; Refer to Figure 18. 4 µs |
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