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TUSB1146 Datasheet(PDF) 12 Page - Texas Instruments |
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TUSB1146 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 68 page ![]() 12 TUSB1146 SLLSFB2 – APRIL 2020 www.ti.com Product Folder Links: TUSB1146 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CTL1 and HPDIN tCTL1_DEBOUNCE CTL1 and HPDIN debounce time when transitioning from H to L. 2 10 ms I2C fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions Refer to Figure 17 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated Refer to Figure 17 0.26 µs tLOW Low period of the I2C clock Refer to Figure 17 0.5 µs tHIGH High period of the I2C clock Refer to Figure 17 0.26 µs tSUSTA Setup time for a repeated START condition Refer to Figure 17 0.26 µs tHDDAT Data hold time Refer to Figure 17 0 µs tSUDAT Data setup time Refer to Figure 17 50 ns tR Rise time of both SDA and SCL signals Refer to Figure 17 120 ns tF Fall time of both SDA and SCL signals Refer to Figure 17 20 × (V(I2C)/5.5 V) 120 ns tSUSTO Setup time for STOP condition Refer to Figure 17 0.26 µs Cb Capacitive load for each bus line 150 pF |
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