S29GL01GS datasheet(73/118 Pages) INFINEON

73 / 118 page

Datasheet

001-98285 Rev. *T

2023-07-17

128 Mb/256 Mb/512 Mb/1 Gb GL-S MIRRORBIT™ Flash

Parallel, 3.0 V

Signal protocols

9.5

Write

9.5.1

Asynchronous Write

When WE# goes Low after CE is LOW, there is a transition from one of the read states to the Write state. If WE# is

LOW before CE# goes LOW, there is a transition from the Standby state directly to the Write state without

beginning a read access.

When CE# is LOW, OE# is HIGH, and WE# goes LOW, a write data transfer begins. Note, OE# and WE# should never

be LOW at the same time to ensure no data bus contention between the host system and memory. When the

asynchronous write cycle timing requirements are met the WE# can go HIGH to capture the address and data

values in to EAC command memory.

Address is captured by the falling edge of WE# or CE#, whichever occurs later. Data is captured by the rising edge

of WE# or CE#, whichever occurs earlier.

When CE# is LOW before WE# goes LOW and stays LOW after WE# goes HIGH, the access is called a WE# controlled

Write. When WE# is HIGH and CE# goes HIGH, there is a transition to the Standby state. If CE# remains LOW and

WE# goes HIGH, there is a transition to the Read with Output Disable state.

When WE# is LOW before CE# goes LOW and remains LOW after CE# goes HIGH, the access is called a CE#

controlled Write. A CE# controlled Write transitions to the Standby state.

If WE# is LOW before CE# goes LOW, the write transfer is started by CE# going LOW. If WE# is LOW after CE# goes

HIGH, the address and data are captured by the rising edge of CE#. These cases are referred to as CE# controlled

write state transitions.

Write followed by Read accesses, in which CE# remains LOW between accesses, requires an address change to

initiate the following read access.

Back to Back accesses, in which CE# remains LOW between accesses, requires an address change to initiate the

second access.

The EAC command memory array is not readable by the host system and has no ASO. The EAC examines the

address and data in each write transfer to determine if the write is part of a legal command sequence. When a

legal command sequence is complete the EAC will initiate the appropriate EA.

9.5.2

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on WE# will not initiate a write cycle.

9.5.3

Logical Inhibit

Write cycles are inhibited by holding OE# at VIL, or CE# at VIH, or WE# at VIH. To initiate a write cycle, CE# and WE#

must be LOW (VIL) while OE# is HIGH (VIH).

S29GL01GS Datasheet(PDF) 73 Page - Infineon Technologies AG