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OMAP3530 Datasheet(PDF) 1 Page - Texas Instruments |
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OMAP3530 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 230 page  www.ti.com 1 OMAP3530/25 Applications Processor 1.1 Features OMAP3530/25 Applications Processor SPRS507 – FEBRUARY 2008 and Program Redirection • OMAP3530/25 Applications Processor: • Hardware Support for Modulo Loop – OMAP™ 3 Architecture Operation – MPU Subsystem • C64x+ L1/L2 Memory Architecture • 600-MHz ARM Cortex™-A8 Core – 32K-Byte L1P Program RAM/Cache (Direct • NEON™ SIMD Coprocessor Mapped) – High Performance Image, Video, Audio – 80K-Byte L1D Data RAM/Cache (2-Way (IVA2.2™) Accelerator Subsystem Set-Associative) • 430-MHz TMS320C64x+™ DSP Core – 64K-Byte L2 Unified Mapped RAM/Cache • Enhanced Direct Memory Access (4-Way Set-Associative) (EDMA) Controller (128 Independent – 32K-Byte L2 Shared SRAM and 16K-Byte L2 Channels) ROM • Video Hardware Accelerators • C64x+ Instruction Set Features – 2D/3D Graphics Accelerator (OMAP3530 – Byte-Addressable (8-/16-/32-/64-Bit Data) Device Only) – 8-Bit Overflow Protection • Tile Based Architecture Delivering 10 MPoly/sec – Bit-Field Extract, Set, Clear • Universal Scalable Shader Engine: – Normalization, Saturation. Bit-Counting Multi-threaded Engine Incorporating – Compact 16-Bit Instructions Pixel and Vertex Shader Functionality – Additional Instructions to Support Complex • Industry Standard API Support: Multiplies OpenGLES 1.1 and 2.0, OpenVG1.0 and • ARM Cortex™-A8 Core Direct3D Mobile – ARMv7 Architecture • Fine Grained Task Switching, Load • Trust Zone® Balancing, and Power Management • Thumb®-2 • Programmable High Quality Image • MMU Enhancements Anti-Aliasing – In-Order, Dual-Issue, Superscalar – Fully Software-Compatible With C64x and Microprocessor Core ARM9™ – NEON™ Multimedia Architecture • Advanced Very-Long-Instruction-Word (VLIW) – Over 2x Performance of ARMv6 SIMD TMS320C64x+™ DSP Core – Supports Both Integer and Floating Point – Eight Highly Independent Functional Units SIMD • Six ALUs (32-/40-Bit), Each Supports – Jazelle® RCT Execution Environment Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Architecture Arithmetic per Clock Cycle – Dynamic Branch Prediction with Branch • Two Multipliers Support Four 16 x 16-Bit Target Address Cache, Global History Multiplies (32-Bit Results) per Clock Buffer, and 8-Entry Return Stack Cycle or Eight 8 x 8-Bit Multiplies (16-Bit – Embedded Trace Macrocell (ETM) Support Results) per Clock Cycle for Non-Invasive Debug – Load-Store Architecture With Non-Aligned Support • ARM Cortex™-A8 Memory Architecture: – 64 32-Bit General-Purpose Registers – 16K-Byte Instruction Cache (4-Way Set-Associative) – Instruction Packing Reduces Code Size – 16K-Byte Data Cache (4-Way – All Instructions Conditional Set-Associative) – Additional C64x+™ Enhancements – 256K-Byte L2 Cache • Protected Mode Operation • Endianess: ARM Big Endian, DSP Little Endian • Exceptions Support for Error Detection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. is a trademark of ~ Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the Copyright © 2008, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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